Protocol Modeling with Hierarchical FSMs and the Discrete Event Domain

This model demonstrates the use of the discrete event (DE) domain and hierarchical finite state machines (FSMs) to model the alternating bit protocol (ABP). ABP [2] is a simple mechanism for achieving reliable, ordered delivery of messages over channels with unreliable delivery and variable delay. The top level of the model, which operates in the DE domain, is shown below with a panel that controls the execution of the model.

The components in the model include:

Message source. This is a DE atomic actor with a parameter MaxDelay. After execution starts, it will wait for a random delay uniformly distributed between 0 and MaxDelay, and then send a request to the sender. When it receives a next from the sender, it will again wait for a random delay uniformly distributed between 0 and MaxDelay, and then send a new msgIn with sequence number increased by one to the sender. In this demo, MaxDelay is set to 0.5.

Timer. The timer has an input setTimer of type DoubleToken. The value of the input token gives the delay before the next timer expire. The timer is reset every time it gets an input token.

Channel. The channel models an unreliable connection in a packet switching network. It queues the input packets, drops and delays the packets randomly. A channel has three parameters: DropRate, MinDelay and MaxDelay. DropRate is the probability that an input packet gets dropped. Packet delay in the channel is uniformly distributed between MinDelay and MaxDelay.

Plot. The plot shows the result of data transmission. In the plot, the red data gives the sequence number of the messages coming out from the receiver. The blue data gives the sequence number of the messages going to the sender. The third data is the "alternating bit" that the protocol uses to number the packets going through the channel.

Sender. The sender implements the sending part of ABP and is a hierarchical FSM. The top level is a 3-state FSM.

The top level FSM starts in the Connecting state. This state refines to the following FSM:

This FSM starts in the Init state. When a request from the message source is received, the FSM sends a special packet (with sequence number -1) to the receiver, sets the timer, and goes to the Wait state. If there is no acknowledgement from the receiver before the timer expires, the FSM sends the special packet again, remains in the Wait state, and waits for the next timeout or acknowledgement from the receiver. If an acknowledgement is not received within five tries, the FSM goes to the Fail state and sends an error event to the top level FSM. Otherwise the FSM goes to the Success state and sends a connected event to the top level.

If connection fails, the top level FSM goes to the Failed state and stops. Otherwise it sends a next event to the message source, and goes to the Sending state, which refines to the following FSM:

This FSM starts in state S0. When a message from the message source is received, the FSM will stay in its current state, tag the message with an additional bit (0 in state S0, 1 in S1, hence the term "alternating bit") to form a packet, and try repeatedly to send the packet until the receiver acknowledges. When the receiver acknowledges, the FSM sends a next event to the message source, and goes to the other state.

Receiver. The receiver is a flat FSM as shown below:

The receiver starts in state Init. In this state, the FSM acknowledges the special packet (with sequence number -1) that the sender sends in trying to establish connection. When a packet tagged with bit 0 is received, the FSM acknowledges the packet, sends the message in the packet to msgOut, then goes to state S1. In state S1, the FSM acknowledges any packet tagged with bit 0. When a packet tagged with bit 1 is received, the FSM acknowledges the packet, sends the message in the packet to msgOut, then goes to state S0. In state S0, the FSM acknowledges any packet tagged with bit 1 while waiting for a packet tagged with bit 0.

Discussion

The purpose of this demo is to show:

References

  1. A. Girault, B. Lee, and E. A. Lee, ``Hierarchical Finite State Machines with Multiple Concurrency Models,'' April 13, 1998.
  2. J. Walrand, and P. Varaiya, ``High-Performance Communication Networks,'' pages 69-72, Morgan Kaufmann Publishers, Inc., 1996.

Last Updated: $Date: 2004/06/21 20:17:03 $