Ptolemy Project Papers for 1998

  1. E. A. Lee and A. Sangiovanni-Vincentelli, ``A Framework for Compa ring Models of Computation,'', IEEE Transactions on CAD, Vol. 17, No. 12, December 1998.
    (Revised from ERL Memorandum UCB/ERL M97/11, University of California, Berkeley, CA 94720, January 30, 1997).
  2. N. Smyth, ``Communicating Sequential ProcessesDomain in Ptolemy II,'' MS Report, UCB/ERL Memorandum M98/70, Dept. of EECS, University of California, Berkeley, CA 94720, December 1998.
  3. J. Liu, ``Continuous Time and Mixed-Signal Simulation in Ptolemy II,'' MS Report, UCB/ERL Memorandum M98/74, Dept. of EECS, University of California, Berkeley, CA 94720, December 1998.
  4. S.-P. Chang, ``System-Level Modeling and Evaluation of Network Protocols,'' MS Report, UCB/ERL Memorandum M98/73, University of California, Berkeley, CA 94710, December 16, 1998.
  5. M. Goel, ``Process Networks in Ptolemy II'' MS Report, ERL Technical Report UCB/ERL No. M98/69, University of California, Berkeley, CA 94720, December 16, 1998.
  6. J. L. Pino and K. Kalbasi, ``Cosimulating Synchronous DSP Applications with Analog RF Circuits,'' presented at the Thirty-Second Annual Asilomar Conference on Signals, Systems, and Computers, November, 1998.
  7. B. Lee and E. A. Lee, ``Interaction of Finite State Machines with Concurrency Models,'' Proc. of Thirty Second Annual Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, November 1998.
  8. E. A. Lee, ``Overview of the Ptolemy Project'', ERL Technical Report UCB/ERL No. M98/71, University of California, Berkeley, CA 94720, November 23, 1998.This paper has been superseded by Technical Memorandum UCB/ERL M01/11, March 6, 2001, also entitled Overview of the Ptolemy Project
  9. J. Davis, R. Galicia, M. Goel, C. Hylands, E.A. Lee, J. Liu, X. Liu, L. Muliadi, S. Neuendorffer, J. Reekie, N. Smyth, J. Tsay and Y. Xiong, ``Heterogeneous Concurrent Modeling and Design in Java,'' Technical Report UCB/ERL No. M98/72, University of California, Berkeley, CA 94720, November 23, 1998.
  10. R. Gupta, Kiran and E. A. Lee, ``Computationally Efficient Version of the Decision Feedback Equalizer,'' to appear in ICASSP 99, September 1998.
  11. E. K. Pauer, C. S. Myers, P. D. Fiore, J. M. Smith, C. M. Crawford, E. A. Lee, J. Lundblad and C. Hylands, ``Algorithm Analysis and Mapping Environment for Adaptive Computing Systems,'' Presented at the Second Annual Workshop on High Performance Embedded Computing, MIT Labs, Lexington, MA, September, 1998.
  12. H. J. Reekie and E. A. Lee, ``The Tycho Slate: Complex Drawing and Editing in Tcl/Tk,'' April 27, 1998. Submitted to the Sixth Annual Tcl/Tk Conference, September 14-18, 1998, San Diego, California.
  13. S. S. Bhattacharyya, S. Sriram, and E. A. Lee, ``Resynchronization for multiprocessor DSP implementation - part 1: Maximum-throughput resynchronization.'' Tech. Rep., Digital Signal Processing Laboratory, University of Maryland, College Park, July 1998. Revised from Memorandum UCB/ERL 96/55, Electronics Research Laboratory, University of California at Berkeley, October, 1996.
  14. S. S. Bhattacharyya, S. Sriram, and E. A. Lee, ``Resynchronization for multiprocessor DSP implementation - part 2: Latency-constrained resynchronization.'' Tech. Rep., Digital Signal Processing Laboratory, University of Maryland, College Park, July 1998. Revised from Memorandum UCB/ERL 96/56, Electronics Research Laboratory, University of California at Berkeley, October, 1996.
  15. M. Williamson ``Synthesis of Parallel Hardware Implementations from Synchronous Dataflow Graph Specifications'' Ph.D. thesis, Memorandum UCB/ERL M98/45, Electronics Research Laboratory, University of California, Berkeley, May, 1998.
  16. A. Girault, B. Lee, and E. A. Lee, ``Hierarchical Finite State Machines with Multiple Concurrency Models,'' April 13, 1998 (revised from Memorandum UCB/ERL M97/57, Electronics Research Laboratory, University of California, Berkeley, CA 94720, August 1997).
  17. B. Lee and E. A. Lee, ``Hierarchical Concurrent Finite State Machines in Ptolemy,'' Proc. of International Conference on Application of Concurrency to System Design, p. 34-40, Fukushima, Japan, March 1998.
  18. J. Liu, M. Lajolo, and A. Sangiovanni-Vincentelli, ``Software Timing Analysis Using SW/HW Cosimulation and Instruction Set Simulator,'' Proc. of the Sixth International Workshop on Hardware/Software Codesign, p. 65-70, Seattle, Washington, March 1998.
  19. S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee, ``Synthesis of Embedded Software from Synchronous Dataflow Specifications,'' Invited paper, to appear in J. of VLSI Signal Processing, 1998.
  20. E. A. Lee and D. G. Messerschmitt, ``Engineering an Education for the Future,'' IEEE Computer Magazine, Vol. 31, No. 1, January, 1998.