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Reinaldo Romero
On-Chip Networks |
Weekly Updates
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Week 1
My first week was really busy and I got to work right away. I meet my mentor, Alessandro Pinto, for the first time and we set some goals and planned out how my project would progress. My project is dependent on knowledge of Verilog HDL, so I read tutorials and lecture notes of Verilog that I found from various university websites. Verilog HDL has a syntax that resembles C, which I found to be helpful. In addition I read over some digital design material from some of my own lecture notes. I obtained printouts of the articles from the bibliography of my project assignment and began to look over them as well.
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Week 2
I got a hold of plenty of Verilog HDL references from Alessandro. Moreover, my project involves doing a comparison between present technologies and future technologies of on-chip networks so I also started to read various articles on optical interconnections and 3D chip stacking technologies that Alessandro had recommended. I found these publications to be really interesting and eye opening. I took the time to take notes of the articles for future reference. Nevertheless, my focus was still on getting a firm grasp of the HDL and I did this by reading the books on Verilog that Alessandro gave me. Verilog has the ability of doing digital logic design at different levels. I had to learn to distinguish between them and especially focus on the Register Transfer Level (RTL) which is what I will be using.
I received access to the Verilog program towards the end of the week. Alessandro showed me around the program and the tools that I would be using. Then, I started to get my feet wet writing some modules in Verilog such as half adders, full adders, and multiplexors. As with any programming language your first programs, or in this case modules did not simulate at first but this allowed me to apply debugging techniques which did improve my modules. I worked on Saturday for a few hours and finished the week with a few modules that could simulate. :-)
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Week 3
This was a busy week. To study the interconnections existing in an on-chip network I need an on-chip network. The first step in building an on-chip network is to build some memory elements. I began to work on the FIFO (First In, First Out) memory chips this week. Alessandro would be away for a number of days so he and I met each day until his departure to review concepts and begin programming the FIFO. The FIFO first needs some finite state machines (FSMs) to implement the write and read processes. This would be my task for the remainder of the week. The experience I had last week with Verilog was a good foundation to begin programming the FSMs but I read more on programming FSMs in Verilog because there are set principals that must be adhered to when creating FSMs.
I could have programmed them using the function technique where the next state is a function of the present state and the input or it could be programmed using three always statements that handle the asynchronous/synchronous events, determine the next state, and evaluate the output(s). I decided to make the FSMs using the three always statements technique. The write and read FSMs are very similar machines so when I successfully make one the other should come natural. At the end of the week I had the write module done but it had a few errors when it was compiled. The errors were fixed but the test bench had port errors in the instantiation of the write module.
My goals for next week are to have the test bench done and working and to mirror my work for the write state machine onto the read state machine. I will analyze the test bench to make sure that it fully tests the state machines for all possible glitches and hazards. I will be communicating with my mentor over the phone and continue developing the parts for the on-chip network.
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Week 4
I have the read and write state machines completed. Making the read state machine was a lot easier because it was very much similar to the write state machine. The waveforms for the inputs and output, as well as the address counter look great. However, when tracing the present and next state signals I get high impedance signals. I have consulted with my mentor as to why this is happening. For the time being I have begun to work on another component to the on-chip network, memory modules. In this module I will try to use an external file to read from and write to. Using an external file will make this a smoother project. My goal for next week is to continue completing the components that are necessary for the FIFO. I will also work on the other parts to the network such as the controller and the cross bar.
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Week 5
I started this week by working on my memory module. In Verilog a memory can be modeled as a two dimension array. I modeled the memory using a behavioral model that declares an array of register variables. Words in the array can then be accessed by calling out the content of an address in the array. The memory module came together nicely. I used J. Bhasker’s Verilog HDL Synthesis, A Practical Primer to help me model this memory module. When the FIFOs are built, these memories will be used again and again to help model the router.
After having the memory done I went to work on the Xbar (crossbar) for my router. I did not begin putting the FIFO together because the FSMs were still being looked over by Alessandro. Getting back to the Xbar, it needs to be able to route the data from the FIFOs to the corresponding output destination which is determined by two filters. The two filters dictate on which route the data will be placed and once it gets to the multiplexers, which will be passed on to the output port. I chose to design the Xbar by modeling multiplexers (mux) and demultiplexer (demux), and then instantiating these modules to construct the Xbar. This hierarchical design will make for a cleaner code that will be easier to alter if need be and it can be easily understood by others. My Xbar design was a success and I will be getting back to putting the FIFO together. My goals for next week are to get the FIFO put together and to move on to putting the whole router together. Alessandro has begun working on the controller that will provide the two filter (or selectors) signals mentioned earlier.
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Week 6
It turns out that my simulator software was the reason why the FSMs were not simulating properly. After using a different simulator, Alessandro was able to confirm that all was well with my FSMs and that my simulator was the actual source of the program, not my coding. My read and write FSMs were now working. I worked on putting the FSMs and the memory module together to ‘give life’ to the FIFO. This required me to change the parameters on my FSM and memory modules to match the FIFO design. After making a FIFO module, I had a number of errors with port assignments and data types. I was able to compile my FIFO model. However, simulation was another story. The FIFO does not function properly. When I reviewed the FSMs they still work properly so I suspect that the memory module was altered by mistake and now needs to be fixed so that the FIFO can work. Also, I used an external file to send data inputs into the testbench and the command $readmem was giving me errors. To fix this I decided to input data values manually with the external file. Nevertheless, the FIFO and memory module are not behaving as they should. My goal for next week is to resolve this issue and have the FIFO working so the router can be connected together and we can complete testing on the on-chip network.
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