Citation
Jan Reineke, Johannes Doerfert. "Architecture-Parametric Timing Analysis". Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Richard West (ed.), IEEE, 189--200, April, 2014.

Abstract
Platforms are families of microarchitectures that implement the same instruction set architecture but that differ in architectural parameters, such as frequency, memory latencies, or memory sizes. The choice of these parameters influences execution time, implementation cost, and energy consumption. In this paper, we introduce the first general framework for architecture-parametric timing analysis (APTA). APTA computes an expression that bounds the worst-case execution time (WCET) of a program in terms of architectural parameters. This enables to configure a platform, at design or even at run time, in a way that is guaranteed to meet all deadlines, while minimizing implementation cost and/or energy consumption. We demonstrate the feasibility of our approach by implementing APTA for a precision-timed (PRET) platform and by evaluating our implementation on M\"alardalen benchmarks.

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  Jan Reineke, Johannes Doerfert. <a
  href="http://chess.eecs.berkeley.edu/pubs/1070.html"
  >Architecture-Parametric Timing Analysis</a>,
  Proceedings of the 20th IEEE Real-Time and Embedded
  Technology and Application Symposium (RTAS), Richard West
  (ed.), IEEE, 189--200, April, 2014.

• Plain text

  Jan Reineke, Johannes Doerfert.
  "Architecture-Parametric Timing Analysis".
  Proceedings of the 20th IEEE Real-Time and Embedded
  Technology and Application Symposium (RTAS), Richard West
  (ed.), IEEE, 189--200, April, 2014.

• BibTeX

  @inproceedings{ReinekeDoerfert14_ArchitectureParametricTimingAnalysis,
      author = {Jan Reineke and Johannes Doerfert},
      title = {Architecture-Parametric Timing Analysis},
      booktitle = {Proceedings of the 20th IEEE Real-Time and
                Embedded Technology and Application Symposium
                (RTAS)},
      editor = {Richard West},
      organization = {IEEE},
      pages = {189--200},
      month = {April},
      year = {2014},
      abstract = {Platforms are families of microarchitectures that
                implement the same instruction set architecture
                but that differ in architectural parameters, such
                as frequency, memory latencies, or memory sizes.
                The choice of these parameters influences
                execution time, implementation cost, and energy
                consumption. In this paper, we introduce the first
                general framework for architecture-parametric
                timing analysis (APTA). APTA computes an
                expression that bounds the worst-case execution
                time (WCET) of a program in terms of architectural
                parameters. This enables to configure a platform,
                at design or even at run time, in a way that is
                guaranteed to meet all deadlines, while minimizing
                implementation cost and/or energy consumption. We
                demonstrate the feasibility of our approach by
                implementing APTA for a precision-timed (PRET)
                platform and by evaluating our implementation on
                M\"alardalen benchmarks.},
      URL = {http://chess.eecs.berkeley.edu/pubs/1070.html}
  }
  

Posted by Jan Reineke on 25 Apr 2014.
Groups: pret
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