An automated exploration framework for FPGA-based soft multiprocessor systems
Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer

Citation
Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer. "An automated exploration framework for FPGA-based soft multiprocessor systems". Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis CODES+ISSS '05, ACM Press (ed.), 273 - 278, September, 2005.

Abstract
FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA. The multiprocessor can be customized for a target application to achieve high performance. Modern FPGAs provide the capacity to build a variety of micro-architectures composed of 20-50 processors, complex memory hierarchies, heterogeneous interconnection schemes and custom co-processors for performance critical operations. However, the diversity in the architectural design space makes it difficult to realize the performance potential of these systems. In this paper we develop an exploration framework to build efficient FPGA multiprocessors for a target application. Our main contribution is a tool based on Integer Linear Programming to explore micro-architectures and allocate application tasks to maximize throughput. Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.

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Citation formats

• HTML

  Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer.
  <a
  href="http://chess.eecs.berkeley.edu/pubs/115.html"
  >An automated exploration framework for FPGA-based soft
  multiprocessor systems</a>, Proceedings of the 3rd
  IEEE/ACM/IFIP international conference on Hardware/software
  codesign and system synthesis CODES+ISSS '05, ACM Press
  (ed.), 273 - 278, September, 2005.

• Plain text

  Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer.
  "An automated exploration framework for FPGA-based soft
  multiprocessor systems". Proceedings of the 3rd
  IEEE/ACM/IFIP international conference on Hardware/software
  codesign and system synthesis CODES+ISSS '05, ACM Press
  (ed.), 273 - 278, September, 2005.

• BibTeX

  @inproceedings{JinSatishRavindranKeutzer05_AutomatedExplorationFrameworkForFPGAbasedSoftMultiprocessor,
      author = {Yujia Jin and Nadathur Satish and Kaushik
                Ravindran and Kurt Keutzer},
      title = {An automated exploration framework for FPGA-based
                soft multiprocessor systems},
      booktitle = {Proceedings of the 3rd IEEE/ACM/IFIP international
                conference on Hardware/software codesign and
                system synthesis CODES+ISSS '05},
      editor = {ACM Press},
      pages = {273 - 278},
      month = {September},
      year = {2005},
      abstract = {FPGA-based soft multiprocessors are viable system
                solutions for high performance applications. They
                provide a software abstraction to enable quick
                implementations on the FPGA. The multiprocessor
                can be customized for a target application to
                achieve high performance. Modern FPGAs provide the
                capacity to build a variety of micro-architectures
                composed of 20-50 processors, complex memory
                hierarchies, heterogeneous interconnection schemes
                and custom co-processors for performance critical
                operations. However, the diversity in the
                architectural design space makes it difficult to
                realize the performance potential of these
                systems. In this paper we develop an exploration
                framework to build efficient FPGA multiprocessors
                for a target application. Our main contribution is
                a tool based on Integer Linear Programming to
                explore micro-architectures and allocate
                application tasks to maximize throughput. Using
                this tool, we implement a soft multiprocessor for
                IPv4 packet forwarding that achieves a throughput
                of 2 Gbps, surpassing the performance of a
                carefully tuned hand design.},
      URL = {http://chess.eecs.berkeley.edu/pubs/115.html}
  }
  

Posted by Kaushik Ravindran on 15 May 2006.
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