An FPGA-Based Soft Multiprocessor System for IPv4 Packet Forwarding
Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer

Citation
Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer. "An FPGA-Based Soft Multiprocessor System for IPv4 Packet Forwarding". Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL-05), 487-492, August, 2005.

Abstract
To realize high performance, embedded applications are deployed on multiprocessor platforms tailored for an application domain. However, when a suitable platform is not available, only few application niches can justify the increasing costs of an IC product design. An alternative is to design the multiprocessor on an FPGA. This retains the programmability advantage, while obviating the risks in producing silicon. This also opens FPGAs to the world of software designers. In this paper, we demonstrate the feasibility of FPGA-based multiprocessors for high performance applications. We deploy IPv4 packet forwarding on a multiprocessor on the Xilinx Virtex-II Pro FPGA. The design achieves a 1.8 Gbps throughput and loses only 2.6X in performance (normalized to area) compared to an implementation on the Intel IXP-2800 network processor. We also develop a design space exploration framework using Integer Linear Programming to explore multiprocessor configurations for an application. Using this framework, we achieve a more efficient multiprocessor design surpassing the performance of our hand-tuned solution for packet forwarding.

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Citation formats

• HTML

  Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer.
  <a
  href="http://chess.eecs.berkeley.edu/pubs/116.html"
  >An FPGA-Based Soft Multiprocessor System for IPv4 Packet
  Forwarding</a>, Proceedings of the 15th International
  Conference on Field Programmable Logic and Applications
  (FPL-05), 487-492, August, 2005.

• Plain text

  Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer.
  "An FPGA-Based Soft Multiprocessor System for IPv4
  Packet Forwarding". Proceedings of the 15th
  International Conference on Field Programmable Logic and
  Applications (FPL-05), 487-492, August, 2005.

• BibTeX

  @inproceedings{RavindranSatishJinKeutzer05_FPGABasedSoftMultiprocessorSystemForIPv4PacketForwarding,
      author = {Kaushik Ravindran and Nadathur Satish and Yujia
                Jin and Kurt Keutzer},
      title = {An FPGA-Based Soft Multiprocessor System for IPv4
                Packet Forwarding},
      booktitle = {Proceedings of the 15th International Conference
                on Field Programmable Logic and Applications
                (FPL-05)},
      pages = {487-492},
      month = {August},
      year = {2005},
      abstract = {To realize high performance, embedded applications
                are deployed on multiprocessor platforms tailored
                for an application domain. However, when a
                suitable platform is not available, only few
                application niches can justify the increasing
                costs of an IC product design. An alternative is
                to design the multiprocessor on an FPGA. This
                retains the programmability advantage, while
                obviating the risks in producing silicon. This
                also opens FPGAs to the world of software
                designers. In this paper, we demonstrate the
                feasibility of FPGA-based multiprocessors for high
                performance applications. We deploy IPv4 packet
                forwarding on a multiprocessor on the Xilinx
                Virtex-II Pro FPGA. The design achieves a 1.8 Gbps
                throughput and loses only 2.6X in performance
                (normalized to area) compared to an implementation
                on the Intel IXP-2800 network processor. We also
                develop a design space exploration framework using
                Integer Linear Programming to explore
                multiprocessor configurations for an application.
                Using this framework, we achieve a more efficient
                multiprocessor design surpassing the performance
                of our hand-tuned solution for packet forwarding.},
      URL = {http://chess.eecs.berkeley.edu/pubs/116.html}
  }
  

Posted by Kaushik Ravindran on 15 May 2006.
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