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Accelerating Applications Using TIPI Sub-RISC Processing Elements
Scott Weber, Kaushik Ravindran, Andrew Mihal, Kurt Keutzer

Citation
Scott Weber, Kaushik Ravindran, Andrew Mihal, Kurt Keutzer. "Accelerating Applications Using TIPI Sub-RISC Processing Elements". Unpublished article, May, 2006.

Abstract
We introduce the TIPI sub-RISC architecture and a supporting infrastructure for designing, programming, analyzing, and implementing TIPI sub-RISC processing elements. The TIPI sub-RISC architectural abstraction encapsulates programmable architectures ranging from hard-wired data paths to RISC/VLIW processors. Although RTL design can capture TIPI processing elements, the TIPI infrastructure substantially increases design entry productivity and provides a 100-1000x increase in simulation performance when compared to RTL design. We have used the TIPI infrastructure to design two processors to accelerate an MP3 decoder. The TIPI processors achieved speedups up to 26x over the corresponding functions in software. The TIPI framework also provides a path to implementation using RTL synthesis. We used this path to implement the system on the Xilinx ML-310 FPGA platform. The main program was executed on the PowerPC core and the TIPI accelerators were built on the Virtex-II Pro 2VP30 FPGA.

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Citation formats  
  • HTML
    Scott Weber, Kaushik Ravindran, Andrew Mihal, Kurt Keutzer.
    <a
    href="http://chess.eecs.berkeley.edu/pubs/117.html"
    ><i>Accelerating Applications Using TIPI Sub-RISC
    Processing Elements</i></a>, Unpublished
    article,  May, 2006.
  • Plain text
    Scott Weber, Kaushik Ravindran, Andrew Mihal, Kurt Keutzer.
    "Accelerating Applications Using TIPI Sub-RISC
    Processing Elements". Unpublished article,  May, 2006.
  • BibTeX
    @unpublished{WeberRavindranMihalKeutzer06_AcceleratingApplicationsUsingTIPISubRISCProcessingElements,
        author = {Scott Weber and Kaushik Ravindran and Andrew Mihal
                  and Kurt Keutzer},
        title = {Accelerating Applications Using TIPI Sub-RISC
                  Processing Elements},
        month = {May},
        year = {2006},
        abstract = {We introduce the TIPI sub-RISC architecture and a
                  supporting infrastructure for designing,
                  programming, analyzing, and implementing TIPI
                  sub-RISC processing elements. The TIPI sub-RISC
                  architectural abstraction encapsulates
                  programmable architectures ranging from hard-wired
                  data paths to RISC/VLIW processors. Although RTL
                  design can capture TIPI processing elements, the
                  TIPI infrastructure substantially increases design
                  entry productivity and provides a 100-1000x
                  increase in simulation performance when compared
                  to RTL design. We have used the TIPI
                  infrastructure to design two processors to
                  accelerate an MP3 decoder. The TIPI processors
                  achieved speedups up to 26x over the corresponding
                  functions in software. The TIPI framework also
                  provides a path to implementation using RTL
                  synthesis. We used this path to implement the
                  system on the Xilinx ML-310 FPGA platform. The
                  main program was executed on the PowerPC core and
                  the TIPI accelerators were built on the Virtex-II
                  Pro 2VP30 FPGA.},
        URL = {http://chess.eecs.berkeley.edu/pubs/117.html}
    }
    

Posted by Kaushik Ravindran on 15 May 2006.
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