Citation
Mike Butts. "Process Network in Silicon: A High-Productivity, Scalable Platform for High-Performance Embedded Computing". Talk or presentation, 25, November, 2008.

Abstract
Conventional high-performance embedded system technology has reached fundamental scaling limits of single CPU/DSP performance and ASIC/FPGA hardware development productivity. Adapting the SMP multicore programming model from general-purpose computing has serious scaling and reliability issues as well, as shown by work here at Berkeley. Adapting the SIMD progamming model from HPC is not always a good match to increasingly irregular and complex algorithms in video, image and wireless processing. We defined a Structured Object Programming Model, based on the Kahn process network model of computation, specifically for embedded computing. Objects are strictly encapsulated software programs running concurrently on a MIMD array of processors and memories. They communicate and synchronize with one another through a structure of buffered channels, in which every data transfer is a synchronization event. An application is a hierarchy of objects and structure, programmed directly in high-level language, without need for automatic parallelizing compilers or synthesis tools. Having first defined this programming model, we defined a scalable hardware architecture, developed one teraOPS production silicon and an integrated development environment, and delivered it to a number of customers who are designing it into their products. University projects have been using it as well. Developers have found this programming model easy to learn and use, and two to three times as productive as their previous DSP, FPGA or ASIC platforms. A hardware and tools demo will be available after the seminar.

Electronic downloads

• ChessMButts25Nov08.pdf · application/pdf · 1962 kbytes

• HTML

  Mike Butts. <a
  href="http://chess.eecs.berkeley.edu/pubs/510.html"
  ><i>Process Network in Silicon: A
  High-Productivity, Scalable Platform for High-Performance
  Embedded Computing</i></a>, Talk or
  presentation,  25, November, 2008.

• Plain text

  Mike Butts. "Process Network in Silicon: A
  High-Productivity, Scalable Platform for High-Performance
  Embedded Computing". Talk or presentation,  25,
  November, 2008.

• BibTeX

  @presentation{Butts08_ProcessNetworkInSiliconHighProductivityScalablePlatform,
      author = {Mike Butts},
      title = {Process Network in Silicon: A High-Productivity,
                Scalable Platform for High-Performance Embedded
                Computing},
      day = {25},
      month = {November},
      year = {2008},
      abstract = {Conventional high-performance embedded system
                technology has reached fundamental scaling limits
                of single CPU/DSP performance and ASIC/FPGA
                hardware development productivity. Adapting the
                SMP multicore programming model from
                general-purpose computing has serious scaling and
                reliability issues as well, as shown by work here
                at Berkeley. Adapting the SIMD progamming model
                from HPC is not always a good match to
                increasingly irregular and complex algorithms in
                video, image and wireless processing. We defined a
                Structured Object Programming Model, based on the
                Kahn process network model of computation,
                specifically for embedded computing. Objects are
                strictly encapsulated software programs running
                concurrently on a MIMD array of processors and
                memories. They communicate and synchronize with
                one another through a structure of buffered
                channels, in which every data transfer is a
                synchronization event. An application is a
                hierarchy of objects and structure, programmed
                directly in high-level language, without need for
                automatic parallelizing compilers or synthesis
                tools. Having first defined this programming
                model, we defined a scalable hardware
                architecture, developed one teraOPS production
                silicon and an integrated development environment,
                and delivered it to a number of customers who are
                designing it into their products. University
                projects have been using it as well. Developers
                have found this programming model easy to learn
                and use, and two to three times as productive as
                their previous DSP, FPGA or ASIC platforms. A
                hardware and tools demo will be available after
                the seminar.},
      URL = {http://chess.eecs.berkeley.edu/pubs/510.html}
  }
  

Posted by Hiren Patel on 25 Nov 2008.
Groups: chess
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