Citation
Hiren Patel, Ben Lickly, Isaac Liu. "Precision Timed (PRET) Machines". Talk or presentation, 16, April, 2009; Presented at the 8th Biennial Ptolemy Miniconference.

Abstract
The philosophy of the PRET project is that current architectures over-emphasize average case performance, and do not adequatly support bounding worst-case execution times. As a result, we present a thread-interleaved processor with manually managed caches and ISA extensions for dealing with timing. The nature of these timing extensions is to provide lower bounds on segments of code in order to provide a repeatable execution. In order to provide this, it is also important for the programmer to verify through static analysis that the code will not take longer than its lower bound. This is what provides the guarantee that every execution will have the same timing behavior. In real situations, however, it may not always be possible to determine a realistic, safe, worst-case execution time bound. In these cases it is desirable for the hardware to provide some guarantee of an upper bound on execution time. Current research involves development of a time based exception handling mechanism. This includes extensions extensions not only to the architecture and ISA of the processor, but also to the C toolchain to support compilation of code with time based exceptions. This could allow for C code using try-catch type blocks, but that raise exceptions in response to missing timing requirements rather than only in response to functional aspects. This would allow a broader scope of programs to be expressible on top of the PRET architecture.

Electronic downloads

• 06-Patel_PrecisionTimedArchitecture-PRET_Apr09.ppt · application/vnd.ms-powerpoint · 3416 kbytes

• HTML

  Hiren Patel, Ben Lickly, Isaac Liu. <a
  href="http://chess.eecs.berkeley.edu/pubs/555.html"
  ><i>Precision Timed (PRET)
  Machines</i></a>, Talk or presentation,  16,
  April, 2009; Presented at the 8th Biennial Ptolemy
  Miniconference.

• Plain text

  Hiren Patel, Ben Lickly, Isaac Liu. "Precision Timed
  (PRET) Machines". Talk or presentation,  16, April,
  2009; Presented at the 8th Biennial Ptolemy Miniconference.

• BibTeX

  @presentation{PatelLicklyLiu09_PrecisionTimedPRETMachines,
      author = {Hiren Patel and Ben Lickly and Isaac Liu},
      title = {Precision Timed (PRET) Machines},
      day = {16},
      month = {April},
      year = {2009},
      note = {Presented at the 8th Biennial Ptolemy
                Miniconference},
      abstract = {The philosophy of the PRET project is that current
                architectures over-emphasize average case
                performance, and do not adequatly support bounding
                worst-case execution times. As a result, we
                present a thread-interleaved processor with
                manually managed caches and ISA extensions for
                dealing with timing. The nature of these timing
                extensions is to provide lower bounds on segments
                of code in order to provide a repeatable
                execution. In order to provide this, it is also
                important for the programmer to verify through
                static analysis that the code will not take longer
                than its lower bound. This is what provides the
                guarantee that every execution will have the same
                timing behavior. In real situations, however, it
                may not always be possible to determine a
                realistic, safe, worst-case execution time bound.
                In these cases it is desirable for the hardware to
                provide some guarantee of an upper bound on
                execution time. Current research involves
                development of a time based exception handling
                mechanism. This includes extensions extensions not
                only to the architecture and ISA of the processor,
                but also to the C toolchain to support compilation
                of code with time based exceptions. This could
                allow for C code using try-catch type blocks, but
                that raise exceptions in response to missing
                timing requirements rather than only in response
                to functional aspects. This would allow a broader
                scope of programs to be expressible on top of the
                PRET architecture.},
      URL = {http://chess.eecs.berkeley.edu/pubs/555.html}
  }
  

Posted by Christopher Brooks on 17 Apr 2009.
Groups: ptolemy
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