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On-time Network On-Chip: Analysis and Architecture
Dai Bui, Alessandro Pinto, Edward A. Lee

Citation
Dai Bui, Alessandro Pinto, Edward A. Lee. "On-time Network On-Chip: Analysis and Architecture". Technical report, University of California, Berkeley, UCB/EECS-2009-59, May, 2009.

Abstract
Game, multimedia, consumer and control applications demand low power and high performance computing platforms capable of providing real-time services. Multi-core architectures, supported by on-chip networks, are emerging as scalable solutions to fulfill these requirements. However, the increasing number of concurrent applications running on these platforms, and the time-varying nature of their communications give rise to unpredictable delays. We propose simple and flexible on-chip protocol and architecture that provide application level communication services with end-to-end timing guarantees. We prove the correctness of our protocol using analytical models and we validate our implementation using detailed simulations.

Electronic downloads

Citation formats  
  • HTML
    Dai Bui, Alessandro Pinto, Edward A. Lee. <a
    href="http://chess.eecs.berkeley.edu/pubs/591.html"
    ><i>On-time Network On-Chip: Analysis and
    Architecture</i></a>, Technical report, 
    University of California, Berkeley, UCB/EECS-2009-59, May,
    2009.
  • Plain text
    Dai Bui, Alessandro Pinto, Edward A. Lee. "On-time
    Network On-Chip: Analysis and Architecture". Technical
    report,  University of California, Berkeley,
    UCB/EECS-2009-59, May, 2009.
  • BibTeX
    @techreport{BuiPintoLee09_OntimeNetworkOnChipAnalysisArchitecture,
        author = {Dai Bui and Alessandro Pinto and Edward A. Lee},
        title = {On-time Network On-Chip: Analysis and Architecture},
        institution = {University of California, Berkeley},
        number = {UCB/EECS-2009-59},
        month = {May},
        year = {2009},
        abstract = {Game, multimedia, consumer and control
                  applications demand low power and high performance
                  computing platforms capable of providing real-time
                  services. Multi-core architectures, supported by
                  on-chip networks, are emerging as scalable
                  solutions to fulfill these requirements. However,
                  the increasing number of concurrent applications
                  running on these platforms, and the time-varying
                  nature of their communications give rise to
                  unpredictable delays. We propose simple and
                  flexible on-chip protocol and architecture that
                  provide application level communication services
                  with end-to-end timing guarantees. We prove the
                  correctness of our protocol using analytical
                  models and we validate our implementation using
                  detailed simulations.},
        URL = {http://chess.eecs.berkeley.edu/pubs/591.html}
    }
    

Posted by Dai Bui on 28 May 2009.
Groups: ptolemy
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