Citation
Edward A. Lee, Stephen A. Edwards, Sungjun Kim, Isaac Liu, Hiren Patel, Martin Schoeberl. "A disruptive computer design idea: Architectures with repeatable timing". Talk or presentation, 6, October, 2009; IEEE International Conference on Computer Design(ICCD), Squaw Valley, CA.

Abstract
This presentation argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.

Electronic downloads

• PRET_ICCD.pdf · application/pdf · 2465 kbytes

• HTML

  Edward A. Lee, Stephen A. Edwards, Sungjun Kim, Isaac Liu,
  Hiren Patel, Martin Schoeberl. <a
  href="http://chess.eecs.berkeley.edu/pubs/647.html"
  ><i>A disruptive computer design idea:
  Architectures with repeatable timing</i></a>,
  Talk or presentation,  6, October, 2009; IEEE International
  Conference on Computer Design(ICCD), Squaw Valley, CA.

• Plain text

  Edward A. Lee, Stephen A. Edwards, Sungjun Kim, Isaac Liu,
  Hiren Patel, Martin Schoeberl. "A disruptive computer
  design idea: Architectures with repeatable timing".
  Talk or presentation,  6, October, 2009; IEEE International
  Conference on Computer Design(ICCD), Squaw Valley, CA.

• BibTeX

  @presentation{LeeEdwardsKimLiuPatelSchoeberl09_DisruptiveComputerDesignIdeaArchitecturesWithRepeatable,
      author = {Edward A. Lee and Stephen A. Edwards and Sungjun
                Kim and Isaac Liu and Hiren Patel and Martin
                Schoeberl},
      title = {A disruptive computer design idea: Architectures
                with repeatable timing},
      day = {6},
      month = {October},
      year = {2009},
      note = {IEEE International Conference on Computer
                Design(ICCD), Squaw Valley, CA},
      abstract = {This presentation argues that repeatable timing is
                more important and more achievable than
                predictable timing. It describes microarchitecture
                approaches to pipelining and memory hierarchy that
                deliver repeatable timing and promise comparable
                or better performance compared to established
                techniques. Specifically, threads are interleaved
                in a pipeline to eliminate pipeline hazards, and a
                hierarchical memory architecture is outlined that
                hides memory latencies.},
      URL = {http://chess.eecs.berkeley.edu/pubs/647.html}
  }
  

Posted by Isaac Liu on 11 Jan 2010.
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