Citation
Gage Eads, Edward A. Lee, Isaac Liu, Jan Reineke, Hiren Patel. "Deadline Instructions in a PRET Architecture". Talk or presentation, 16, February, 2011; Poster presented at the Ninth Biennial Ptolemy Miniconference, Berkeley, CA.

Abstract
The PRET project aims to improve the timing predictability at all layers of abstraction by carefully reexamining and reworking various architectural and compiler advancements with an eye toward their effects on timing behavior and worst-case bounds. This poster explores the five proposed timing assembly instructions and three C-level constructs that leverage the instructions. In addition, the PRET Simulator v2.0 is discussed.

Electronic downloads

• p02EadsPtolemyMiniConference2011_geads.pdf · application/pdf · 1003 kbytes

• HTML

  Gage Eads, Edward A. Lee, Isaac Liu, Jan Reineke, Hiren
  Patel. <a
  href="http://chess.eecs.berkeley.edu/pubs/818.html"><i>Deadline
  Instructions in a PRET Architecture</i></a>,
  Talk or presentation,  16, February, 2011; Poster presented
  at the <a
  href="http://ptolemy.eecs.berkeley.edu/conferences/11"
  >Ninth Biennial Ptolemy Miniconference</a>,
  Berkeley, CA.

• Plain text

  Gage Eads, Edward A. Lee, Isaac Liu, Jan Reineke, Hiren
  Patel. "Deadline Instructions in a PRET
  Architecture". Talk or presentation,  16, February,
  2011; Poster presented at the <a
  href="http://ptolemy.eecs.berkeley.edu/conferences/11"
  >Ninth Biennial Ptolemy Miniconference</a>,
  Berkeley, CA.

• BibTeX

  @presentation{EadsLeeLiuReinekePatel11_DeadlineInstructionsInPRETArchitecture,
      author = {Gage Eads and Edward A. Lee and Isaac Liu and Jan
                Reineke and Hiren Patel},
      title = {Deadline Instructions in a PRET Architecture},
      day = {16},
      month = {February},
      year = {2011},
      note = {Poster presented at the <a
                href="http://ptolemy.eecs.berkeley.edu/conferences/11"
                >Ninth Biennial Ptolemy Miniconference</a>,
                Berkeley, CA.},
      abstract = {The PRET project aims to improve the timing
                predictability at all layers of abstraction by
                carefully reexamining and reworking various
                architectural and compiler advancements with an
                eye toward their effects on timing behavior and
                worst-case bounds. This poster explores the five
                proposed timing assembly instructions and three
                C-level constructs that leverage the instructions.
                In addition, the PRET Simulator v2.0 is discussed.},
      URL = {http://chess.eecs.berkeley.edu/pubs/818.html}
  }
  

Posted by Christopher Brooks on 18 Feb 2011.
Groups: ptolemy
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