Citation
Isaac Liu. "PTARM Simulator v1.0". University of California, Berkeley, 25, May, 2011.

Abstract
The PRET project is a collaborative effort lead by Prof. Edward A. Lee at U. C. Berkeley, and Prof. Stephen A. Edwards at Columbia University. Our objective is to reintroduce predictable and repeatable timing to real-time embedded processor architectures. We select architectural techniques that deliver performance enhancements, and that preserve timing predictability and repeatability.

The first simulation model of the PRET architecture was a using the SPARC ISA. The simulator can be found at: http://chess.eecs.berkeley.edu/pret/release. The second revision of the Precision Timed Architecture uses the ARM ISA and is named the PTARM (Precision Timed ARM). The simulator can be found at: http://chess.eecs.berkeley.edu/pret/release/ptarm.

Electronic downloads

• http://chess.eecs.berkeley.edu/pret/src/ptarm-1.0/ptarm_simulator.html

• HTML

  Isaac Liu. <a
  href="http://chess.eecs.berkeley.edu/pubs/842.html"
  ><i>PTARM Simulator v1.0</i></a>,
  University of California, Berkeley, 25, May, 2011.

• Plain text

  Isaac Liu. "PTARM Simulator v1.0". University of
  California, Berkeley, 25, May, 2011.

• BibTeX

  @software{Liu11_PTARMSimulatorV10,
      author = {Isaac Liu},
      title = {PTARM Simulator v1.0},
      institution = {University of California, Berkeley},
      day = {25},
      month = {May},
      year = {2011},
      abstract = {The PRET project is a collaborative effort lead by
                Prof. Edward A. Lee at U. C. Berkeley, and Prof.
                Stephen A. Edwards at Columbia University. Our
                objective is to reintroduce predictable and
                repeatable timing to real-time embedded processor
                architectures. We select architectural techniques
                that deliver performance enhancements, and that
                preserve timing predictability and repeatability.
                <p>The first simulation model of the PRET
                architecture was a using the SPARC ISA. The
                simulator can be found at: <a
                href=http://chess.eecs.berkeley.edu/pret/release">http://chess.eecs.berkeley.edu/pret/release</a>.
                The second revision of the Precision Timed
                Architecture uses the ARM ISA and is named the
                PTARM (Precision Timed ARM). The simulator can be
                found at: <a
                href="http://chess.eecs.berkeley.edu/pret/release/ptarm">http://chess.eecs.berkeley.edu/pret/release/ptarm</a>.},
      URL = {http://chess.eecs.berkeley.edu/pubs/842.html}
  }
  

Posted by Christopher Brooks on 17 Jun 2011.
Groups: pret
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