Citation
Isaac Liu. "Precision Timed (PRET) Machines". Talk or presentation, 24, April, 2012.

Abstract
Cyber-Physical Systems (CPS) are integrations of computation with physical processes. An number of applications can potentially benefit from the potential of CPS. However, these systems must be equipped to handle the inherent concurrency and inexorable passage of time of physical processes. The traditional computing abstractions only concern themselves with the functional aspects of a program, and not its timing properties. Thus, nearly every abstraction layer has failed to incorporate time into its semantics; the passage of time is merely a consequence of the implementation. When the temporal properties of the system must be guaranteed, designers must reach beneath the abstraction layers. This not only increases the design complexity and effort, but the designed systems are brittle and extremely sensitive to change. In this work, we re-examine the ISA layer and its affects on microarchitecture design. The ISA defines the contract between software instructions and hardware implementations. However, modern ISAs do not specify timing properties of the instructions as part of the contract, thus, architecture designs have largely implemented techniques that improve average performance at the expense of execution time variability. This leads to imprecise WCET bounds that limit the timing predictability and timing composability of architectures. In order to address the lack of temporal semantics in the ISA, we propose instruction extensions to the ISA that give temporal meaning to the program. The instruction extensions allow programs to specify execution time properties in software that must be observed for any correct execution of the program. In addition, we present the Precision Timed ARM (PTARM) architecture, a realization of Precision Timed (PRET) machines that provide timing predictability and composability without sacrificing performance. PTARM employs a predictable thread-interleaved pipeline with an exposed memory hierarchy that uses scratchpads and a predictable DRAM controller. This removes timing interference amongst the hardware threads, enabling timing composability in the architecture, and provides deterministic execution times for all instructions within the architecture, enabling timing predictability in the architecture. We show that the predictable thread-interleaved pipeline and DRAM controller also achieves better throughput compared to conventional architectures when fully utilized, accomplishing our goal to provide both predictability and performance. To show the applicability of the architecture, we present two applications implemented with the PRET architecture that utilize the predictable execution time and the timing extended ISA to achieve its design requirements. With this work, we aim to provide a deterministic foundation for higher abstraction layers, which enables more efficient designs of safety-critical cyber-physical systems.

Electronic downloads

• liu_2012_dissertation_talk_pret.pdf · application/pdf · 9874 kbytes

• HTML

  Isaac Liu. <a
  href="http://chess.eecs.berkeley.edu/pubs/906.html"
  ><i>Precision Timed (PRET)
  Machines</i></a>, Talk or presentation,  24,
  April, 2012.

• Plain text

  Isaac Liu. "Precision Timed (PRET) Machines". Talk
  or presentation,  24, April, 2012.

• BibTeX

  @presentation{Liu12_PrecisionTimedPRETMachines,
      author = {Isaac Liu},
      title = {Precision Timed (PRET) Machines},
      day = {24},
      month = {April},
      year = {2012},
      abstract = {Cyber-Physical Systems (CPS) are integrations of
                computation with physical processes. An number of
                applications can potentially benefit from the
                potential of CPS. However, these systems must be
                equipped to handle the inherent concurrency and
                inexorable passage of time of physical processes.
                The traditional computing abstractions only
                concern themselves with the functional aspects of
                a program, and not its timing properties. Thus,
                nearly every abstraction layer has failed to
                incorporate time into its semantics; the passage
                of time is merely a consequence of the
                implementation. When the temporal properties of
                the system must be guaranteed, designers must
                reach beneath the abstraction layers. This not
                only increases the design complexity and effort,
                but the designed systems are brittle and extremely
                sensitive to change. In this work, we re-examine
                the ISA layer and its affects on microarchitecture
                design. The ISA defines the contract between
                software instructions and hardware
                implementations. However, modern ISAs do not
                specify timing properties of the instructions as
                part of the contract, thus, architecture designs
                have largely implemented techniques that improve
                average performance at the expense of execution
                time variability. This leads to imprecise WCET
                bounds that limit the timing predictability and
                timing composability of architectures. In order to
                address the lack of temporal semantics in the ISA,
                we propose instruction extensions to the ISA that
                give temporal meaning to the program. The
                instruction extensions allow programs to specify
                execution time properties in software that must be
                observed for any correct execution of the program.
                In addition, we present the Precision Timed ARM
                (PTARM) architecture, a realization of Precision
                Timed (PRET) machines that provide timing
                predictability and composability without
                sacrificing performance. PTARM employs a
                predictable thread-interleaved pipeline with an
                exposed memory hierarchy that uses scratchpads and
                a predictable DRAM controller. This removes timing
                interference amongst the hardware threads,
                enabling timing composability in the architecture,
                and provides deterministic execution times for all
                instructions within the architecture, enabling
                timing predictability in the architecture. We show
                that the predictable thread-interleaved pipeline
                and DRAM controller also achieves better
                throughput compared to conventional architectures
                when fully utilized, accomplishing our goal to
                provide both predictability and performance. To
                show the applicability of the architecture, we
                present two applications implemented with the PRET
                architecture that utilize the predictable
                execution time and the timing extended ISA to
                achieve its design requirements. With this work,
                we aim to provide a deterministic foundation for
                higher abstraction layers, which enables more
                efficient designs of safety-critical
                cyber-physical systems.},
      URL = {http://chess.eecs.berkeley.edu/pubs/906.html}
  }
  

Posted by Patricia Derler on 24 Apr 2012.
Groups: ptpresenters
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