Citation
Isaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward A. Lee. "A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance". Proceedings of the 30th IEEE International Conference on Computer Design (ICCD 2012), October, 2012;

(C) Copyright 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Published version: http://dx.doi.org/10.1109/ICCD.2012.6378622 .

Abstract
We contend that repeatability of execution times is crucial to the validity of testing of real-time systems. However, computer architecture designs fail to deliver repeatable timing, a consequence of aggressive techniques that improve averagecase performance. This paper introduces the Precision-Timed ARM (PTARM), a precision-timed (PRET) microarchitecture implementation that exhibits repeatable execution times without sacrificing performance. The PTARM employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy, including a repeatable DRAM controller. Our benchmarks show an improved throughput compared to a single-threaded in-order five-stage pipeline, given sufficient parallelism in the software.

Electronic downloads

• ptarm-iccd-2012-accepted-version.pdf · application/pdf · 181 kbytes
• http://dx.doi.org/10.1109/ICCD.2012.6378622

• HTML

  Isaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward
  A. Lee. <a
  href="http://chess.eecs.berkeley.edu/pubs/919.html"
  >A PRET Microarchitecture Implementation with Repeatable
  Timing and Competitive Performance</a>, Proceedings of
  the 30th IEEE International Conference on Computer Design
  (ICCD 2012), October, 2012; <p>
  (C) Copyright 2012
  IEEE. Personal use of this material is permitted. Permission
  from IEEE must be obtained for all other uses, in any
  current or future media, including reprinting/republishing
  this material for advertising or promotional purposes,
  creating new collective works, for resale or redistribution
  to servers or lists, or reuse of any copyrighted component
  of this work in other works.
  
  <p>
  Published
  version: <a
  href="http://dx.doi.org/10.1109/ICCD.2012.6378622"
  >http://dx.doi.org/10.1109/ICCD.2012.6378622</a>
  .

• Plain text

  Isaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward
  A. Lee. "A PRET Microarchitecture Implementation with
  Repeatable Timing and Competitive Performance".
  Proceedings of the 30th IEEE International Conference on
  Computer Design (ICCD 2012), October, 2012; <p>
  (C)
  Copyright 2012 IEEE. Personal use of this material is
  permitted. Permission from IEEE must be obtained for all
  other uses, in any current or future media, including
  reprinting/republishing this material for advertising or
  promotional purposes, creating new collective works, for
  resale or redistribution to servers or lists, or reuse of
  any copyrighted component of this work in other works.
  
  <p>
  Published version: <a
  href="http://dx.doi.org/10.1109/ICCD.2012.6378622"
  >http://dx.doi.org/10.1109/ICCD.2012.6378622</a>
  .

• BibTeX

  @inproceedings{LiuReinekeBromanZimmerLee12_PRETMicroarchitectureImplementationWithRepeatableTiming,
      author = {Isaac Liu and Jan Reineke and David Broman and
                Michael Zimmer and Edward A. Lee},
      title = {A PRET Microarchitecture Implementation with
                Repeatable Timing and Competitive Performance},
      booktitle = {Proceedings of the 30th IEEE International
                Conference on Computer Design (ICCD 2012)},
      month = {October},
      year = {2012},
      note = {<p>
  (C) Copyright 2012 IEEE. Personal use of this
                material is permitted. Permission from IEEE must
                be obtained for all other uses, in any current or
                future media, including reprinting/republishing
                this material for advertising or promotional
                purposes, creating new collective works, for
                resale or redistribution to servers or lists, or
                reuse of any copyrighted component of this work in
                other works.
  
  <p>
  Published version: <a
                href="http://dx.doi.org/10.1109/ICCD.2012.6378622"
                >http://dx.doi.org/10.1109/ICCD.2012.6378622</a>
  },
      abstract = {We contend that repeatability of execution times
                is crucial to the validity of testing of real-time
                systems. However, computer architecture designs
                fail to deliver repeatable timing, a consequence
                of aggressive techniques that improve averagecase
                performance. This paper introduces the
                Precision-Timed ARM (PTARM), a precision-timed
                (PRET) microarchitecture implementation that
                exhibits repeatable execution times without
                sacrificing performance. The PTARM employs a
                repeatable thread-interleaved pipeline with an
                exposed memory hierarchy, including a repeatable
                DRAM controller. Our benchmarks show an improved
                throughput compared to a single-threaded in-order
                five-stage pipeline, given sufficient parallelism
                in the software.},
      URL = {http://chess.eecs.berkeley.edu/pubs/919.html}
  }
  

Posted by Michael Zimmer on 22 Aug 2012.
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