Citation
Aviral Shrivastava. "Beyond the Hill of Multicores lies the Valley of Accelerators". Talk or presentation, 30, October, 2012.

Abstract
The power wall has resulted in a sharp turn in processor designs, and they irrevocably went multi-core. Multi-cores are good because they promise higher potential throughput (and never mind the actual performance of your applications). This is because the cores can be made simpler and run at lower voltage resulting in much more power-efficient operation. Even though the performance of single-core is much reduced, the total possible throughput of the system scales with the number of cores. However, the excitement of multi-core architectures will only last so long. This is not only because the benefits of voltage scaling will reduce with decreasing voltage, but also because after some point, making a core simpler will only be detrimental and may actually increase power-efficiency. What next! How do we further improve power-efficiency? Beyond the hill of multi-cores, lies the valley of accelerators. Accelerators: hardware accelerators (e.g., Intel SSE), software accelerators (e.g., VLIW accelerators), reconfigurable accelerators (e.g., FPGAs), programmable accelerators (CGRAs) are some of the foreseeable solutions that can further improve power-efficiency of computation. Among these, we find CGRAs, or Coarse Grain Reconfigurable Arrays a very promising technology. They are slightly reconfigurable (and therefore close to hardware), but are programmable (therefore usable as more general-purpose accelerators). As a result, they can provide power-efficiencies of up to 100 GOps/W, while being relatively general purpose. Although very promising, several challenges remain in compilation for CGRAs, especially because they have very little dynamism in the architecture, and almost everything (including control) is statically determined. In this talk, I will talk about our recent research in developing compiler technology to enable CGRAs as general-purpose accelerators.

Electronic downloads

• dreams-shrivastava-2012.pdf · application/download · 14279 kbytes

• HTML

  Aviral Shrivastava. <a
  href="http://chess.eecs.berkeley.edu/pubs/946.html"
  ><i>Beyond the Hill of Multicores lies the Valley
  of Accelerators</i></a>, Talk or presentation, 
  30, October, 2012.

• Plain text

  Aviral Shrivastava. "Beyond the Hill of Multicores lies
  the Valley of Accelerators". Talk or presentation,  30,
  October, 2012.

• BibTeX

  @presentation{Shrivastava12_BeyondHillOfMulticoresLiesValleyOfAccelerators,
      author = {Aviral Shrivastava},
      title = {Beyond the Hill of Multicores lies the Valley of
                Accelerators},
      day = {30},
      month = {October},
      year = {2012},
      abstract = {The power wall has resulted in a sharp turn in
                processor designs, and they irrevocably went
                multi-core. Multi-cores are good because they
                promise higher potential throughput (and never
                mind the actual performance of your applications).
                This is because the cores can be made simpler and
                run at lower voltage resulting in much more
                power-efficient operation. Even though the
                performance of single-core is much reduced, the
                total possible throughput of the system scales
                with the number of cores. However, the excitement
                of multi-core architectures will only last so
                long. This is not only because the benefits of
                voltage scaling will reduce with decreasing
                voltage, but also because after some point, making
                a core simpler will only be detrimental and may
                actually increase power-efficiency. What next! How
                do we further improve power-efficiency? Beyond the
                hill of multi-cores, lies the valley of
                accelerators. Accelerators: hardware accelerators
                (e.g., Intel SSE), software accelerators (e.g.,
                VLIW accelerators), reconfigurable accelerators
                (e.g., FPGAs), programmable accelerators (CGRAs)
                are some of the foreseeable solutions that can
                further improve power-efficiency of computation.
                Among these, we find CGRAs, or Coarse Grain
                Reconfigurable Arrays a very promising technology.
                They are slightly reconfigurable (and therefore
                close to hardware), but are programmable
                (therefore usable as more general-purpose
                accelerators). As a result, they can provide
                power-efficiencies of up to 100 GOps/W, while
                being relatively general purpose. Although very
                promising, several challenges remain in
                compilation for CGRAs, especially because they
                have very little dynamism in the architecture, and
                almost everything (including control) is
                statically determined. In this talk, I will talk
                about our recent research in developing compiler
                technology to enable CGRAs as general-purpose
                accelerators. },
      URL = {http://chess.eecs.berkeley.edu/pubs/946.html}
  }
  

Posted by David Broman on 6 Nov 2012.
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