Citation
David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian Cai, Aviral Shrivastava, Stephen A. Edwards, Edward A. Lee. "Precision Timed Infrastructure: Design Challenges". In the Proceedings of the Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, 31, May, 2013.

Abstract
In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening consequences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as C lack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.

Electronic downloads

• http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=\&arnumber=6573221. ((Published paper))
• http://www.eecs.berkeley.edu/Pubs/TechRpts/2013/EECS-2013-161.html. (Open Access Tech Report Version)
• broman-et-al-2012-preprint-pret-infrastructure.pdf · application/pdf · 246 kbytes

• HTML

  David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian
  Cai, Aviral Shrivastava, Stephen A. Edwards, Edward A. Lee.
  <a
  href="http://chess.eecs.berkeley.edu/pubs/993.html"
  >Precision Timed Infrastructure: Design
  Challenges</a>, In the Proceedings of the Electronic
  System Level Synthesis Conference (ESLsyn), Austin, Texas,
  USA, 31, May, 2013.

• Plain text

  David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian
  Cai, Aviral Shrivastava, Stephen A. Edwards, Edward A. Lee.
  "Precision Timed Infrastructure: Design
  Challenges". In the Proceedings of the Electronic
  System Level Synthesis Conference (ESLsyn), Austin, Texas,
  USA, 31, May, 2013.

• BibTeX

  @inproceedings{BromanZimmerKimKimCaiShrivastavaEdwardsLee13_PrecisionTimedInfrastructureDesignChallenges,
      author = {David Broman and Michael Zimmer and Yooseong Kim
                and Hokeun Kim and Jian Cai and Aviral Shrivastava
                and Stephen A. Edwards and Edward A. Lee},
      title = {Precision Timed Infrastructure: Design Challenges},
      booktitle = {In the Proceedings of the Electronic System Level
                Synthesis Conference (ESLsyn), Austin, Texas, USA},
      day = {31},
      month = {May},
      year = {2013},
      abstract = {In general-purpose software applications,
                computation time is just a quality factor: faster
                is better. In cyber-physical systems (CPS),
                however, computation time is a correctness factor:
                missed deadlines for hard real-time applications,
                such as avionics and automobiles, can result in
                devastating, life-threatening consequences.
                Although many modern modeling languages for CPS
                include the notion of time, implementation
                languages such as C lack any temporal semantics.
                Consequently, models and programs for CPS are
                neither portable nor guaranteed to execute
                correctly on the real system; timing is merely a
                side effect of the realization of a software
                system on a specific hardware platform. In this
                position paper, we present the research initiative
                for a precision timed (PRET) infrastructure,
                consisting of languages, compilers, and
                microarchitectures, where timing is a correctness
                factor. In particular, the timing semantics in
                models and programs must be preserved during
                compilation to ensure that the behavior of real
                systems complies with models. We also outline new
                research and design challenges present in such an
                infrastructure.},
      URL = {http://chess.eecs.berkeley.edu/pubs/993.html}
  }
  

Posted by David Broman on 10 Jun 2013.
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