PUBLICATIONS

Publications in International Conferences and Journals

• J. G. Pena and A. L. Oliveira, A New Algorithm For The Reduction of Incompletely Specified Finite State Machines , International Conference on Computer Aided Design, San Jose, CA, 1998
• V. M. Manquinho and A. L. Oliveira and J. P. M. Silva, Models and Algorithms for Computing Minimum Size Prime Implicants , Proceedings of the International Workshop on Boolean Problems, Freiberg, Germany, 1998.
• A. L. Oliveira and J. P. M. Silva, Efficient Search Techniques for the Inference of Minimum Size Finite Automata , Proceedings of the 1998 South American Symposium on String Processing and Information Retrieval, Santa Cruz de La Sierra, Bolivia, 1998.
• J. P. M. Silva and V. M. Manquinho and A. L. Oliveira and K. Sakallah Satisfiability-Based Algorithms for 0-1 Integer Programming , International Workshop on Logic Synthesis, Lake Tahoe, CA, 1998.
• J. C. Monteiro and A. L. Oliveira Finite State Machine Decomposition For Low Power , Proceedings of the 1998 ACM/IEEE Design Automation Conference, Los Angeles, CA, 1998.
• R. Murgai and M. Fujita and A. L. Oliveira Using Complementation And Resequencing To Minimize Transitions , Proceedings of the 1998 ACM/IEEE Design Automation Conference, Los Angeles, CA, 1998.
• A. S. Mota and J. C. Monteiro and A. L. Oliveira, Power Optimization of Combinational Modules Using Self-Timed Precomputation , Proceedings of the IEEE International Symposium on Circuits and Systems, Monterey, CA, 1998.
• V. M. Manquinho and P. F. Flores and J. P. M. Silva and A. L. Oliveira, Prime Implicant Computation Using Satisfiability Algorithms , Proceedings of the International Conference on Tools with Artificial Intelligence, ICTAI, Monterey, CA, 1997.
• A. L. Oliveira and L. Carloni and T. Villa and A. Sanviovanni Vincentelli, An implicit formulation for exact BDD minimization of incompletely specified functions, VLSI: Integrated Systems on Silicon, Gramado, Brazil, 1997, Chapman-Hall.
• J. P. M. Silva and A. L. Oliveira, Improving Satisfiability Algorithms with Dominance and Partioning, International Workshop on Logic Synthesis, Lake Tahoe, 1997, CA.
• Arlindo L. Oliveira and Stephen Edwards, Limits of Exact Algorithms For Inference of Minimum Size Finite State Machines, Proceedings of the Seventh International Workshop in Algorithmic Learning Theory, Lecture Notes in Artificial Intelligence 1160, pp. 59-66, Sydney, Australia, October 1996. Springer.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Using the Minimum Description Length Principle to Infer Reduced Ordered Decision Graphs, Machine Learning, 25, pp. 23-50, 1996.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Inferring reduced ordered decision graphs of minimal description length, Proceedings of the Twelfth International Conference in Machine Learning}, pages 421--429. Morgan Kaufmann, 1995.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Inferring Reduced Ordered Decision Graphs of Minimal Description Length, ML94 Workshop on Applications of MDL, New Brunswick, NJ, July 1994.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Learning Complex Boolean Functions : Algorithms and Applications, Advances in Neural Information Processing Systems 6, Morgan Kaufmann, Denver, CO, December 1993
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, What Can Boolean Networks Learn ?, Third International Workshop on Computational Learning Theory and Natural Learning Systems, Madison, Winsconsin, August 1992.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Constructive Induction Using a Non-Greedy Strategy for Feature Selection, Proceedings of the Ninth International Conference in Machine Learning, Aberdeen, Scotland, June 1992.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, LSAT: An Algorithm for the Synthesis of Threshold Gate Networks, 1991 International Conference in Computer Aided Design, Santa Clara, CA, November 1991.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Learning Concepts by Synthesizing Minimal Threshold Gate Networks Proceedings of the Eight International Workshop in Machine Learning, Chicago, IL, June 1991.
• Arlindo L. Oliveira, J.P. Teixeira, I.C. Teixeira, C.F.B. Almeida, F. Gonçalves, ``Test Preparation for MOS Digital Circuits, Using Heuristics for Reliable Fault Simulation'', Proc. Int. Conf. on CAD/CAM and AMT in Israel, Jerusalem, Dec., 1989.
• Arlindo L. Oliveira, N. R. Rua, P. A. Bicudo, J. A. Grácio, J. C. Teixeira, and C. B. Almeida, Bottom-up methodology for test preparation and refinement, ISCAS-89, pp. 949-952, Portland, OR, May 1989.
• Arlindo L. Oliveira, N. R. Rua, P. A. Bicudo, J. A. Grácio, J. C. Teixeira, and C. B. Almeida, Test preparation and fault analysis using a bottom-up methodology, European Test Conference, pp. 168-174, April 1989.
• Arlindo L. Oliveira, J. C. Teixeira, C. B. Almeida, J.A. Grácio, P. A. Bicudo, and N. R. Rua, Bottom-up testing methodology for VLSI, IEEE Custom Integrated Circuits Conference, pages 16.6.1--4, May 1988.
• Arlindo L. Oliveira, F. V. Coito, L. M. Silveira, J. M. Lemos, and Jorge S. Marques, A microprocessor implementation of self-tunning controllers, Second IFAC Symposium on Adaptive Systems for Control and Signal Processing}, Lund, Sweden, June 1986.

Publications in National Conferences and Workshops

• Arlindo L. Oliveira, J. C. Teixeira, C. B. Almeida, and N. R. Rua, Swich-level concurrent fault simulation of digital circuits. Terceiro Simpósio de Electrónica das Telecomunicações, pages 6-10, Porto, Portugal, May 1988.
• Arlindo L. Oliveira, J. C. Teixeira, C. B. Almeida, J.A. Grácio, P.A. Bicudo, and N. R. Rua. Metodologia de teste de circuitos integrados para apoio ao projecto de circuitos, Terceiro Workshop Nacional sobre Engenharia de Telecomunicações, Computadores e Informática, Aveiro, Portugal, November 1987.
• Arlindo L. Oliveira and M. J. Lança, Módulo de controlo de um circuito integrado para telefone inteligente em tecnologia CMOS, Segundo Workshop Nacional Sobre Tecnologia de Telecomunicações, Vimeiro, Portugal, October 1985.

Technical Reports and Others

• Arlindo L. Oliveira, Tiziano Villa, Luca Carloni, Alberto Sangiovanni-Vincentelli, Exact Minimization of Boolean Decision Diagrams Using Implicit Techniques technical report UCB/ERL M96/16.
• Arlindo L. Oliveira, Stephen Edwards and Alberto Sangiovanni-Vincentelli, Inference of State Machines from Examples of Behavior UCB/ERL technical report M95/12.
• Arlindo L. Oliveira, Inductive Learning by Selection of Minimal Complexity Representations, UCB/ERL Technical Report M94/97, my UC Berkeley PhD dissertation.
• Arlindo L. Oliveira and Alberto Sangiovanni-Vincentelli, Empirical Learning of Boolean Functions Using Two-Level Logic Synthesis, UCB/ERL Internal Report, July 1991.
• Arlindo L. Oliveira, A simulação concorrente de faltas em circuitos integrados usando modelos ao nível de interruptor, my MSc thesis, Instituto Superior Técnico.
• Arlindo L. Oliveira¸ A. Grácio, P. Bicudo, J.P. Teixeira, Layout-Dependent Fault Testing: Final Report, 991 ESPRIT Project Deliverable, Workpackage 7 (INESC), March 1989.
• Arlindo L. Oliveira, N.R. Rua, C.F.B. Almeida, J.P.C. Teixeira, SWIFT, a SWitch-level Fault simulator with Timing information, Release 1.0, Esprit 991 Project Report, Sept. 1988.
• Arlindo L. Oliveira, J.P.C. Teixeira, P. Bicudo, A. Grácio, Node and Fault Modelling, 991 ESPRIT Project Deliverable, Workpackage 7 (INESC), Junho de 1987.
• Arlindo L. Oliveira, C.F.B. Almeida, J.P.C. Teixeira, An Algorithm for Switch-Level Fault Simulation, 991 ESPRIT Project Deliverable, Workpackage 7 (INESC), Junho de 1987.
• Arlindo L. Oliveira, I.C. Teixeira, J.P. Teixeira, C.F.B. Almeida, A. F. Gon\c calves, Introducing Circuit Knowledge in Switch-Level Simulation, INESC, Int. Rep., April, 1989.
• Arlindo L. Oliveira, J.P.C. Teixeira, P. Bicudo, A. Grácio, C.F.B. Almeida, L.M. Vidigal, A Bottom-up Testing Methodology for VLSI, INESC, Rel. Interno, Maio de 1987.