Measurement and Modeling of Transistor Current Mismatch in Analog ICs
, in Proceedings of the International Conference on Computer Aided Design, Nov. 1994, San Jose, Cal., pp 272-
277 (with E. Felt and A. Sangiovanni- Vincentelli)
Measurement and Modeling of Transistor Current Mismatch in Analog ICs
, in Proceedings of the International Conference on Computer Aided Design, Nov. 1994, San Jose, Cal., pp 272-
277
A Study of Composition Schemes for Mixed Apply/Compose Based Construction of
ROBDDs , in Proceedings of the 9th International Conference on VLSI Design, Jan. 1996,
Bangalore, India.
Engineering Change in a Non-Deterministic FSM Setting,
in Proceedings of the 33rd Design Automation Conference, June 1996, Las Vegas, Nevada,
pp 451-456.
Decomposition Techniques for Efficient ROBDD Construction ,
in Proceedings of Formal Methods in Computer-Aided Design, November 1996, San Jose, CA
Partitioned-ROBDDs -- A Compact, Canonical and Efficiently Manipulable Representation for Boolean Functions ,
in Proceedings of the International Conference on Computer Aided Design, Nov. 1996, San Jose, CA.
Formal Verification of Combinational Circuits ,
in Proceedings of the 10th International Conference on VLSI Design, Jan. 1997, Hyderabad, India
pp 218-225.
On Synthesizing Pass Transistor Networks ,
in Proceedings of the ACM/IEEE International Workshop on Logic Synthesis, May 1997, Tahoe City, CA
A Survey of Combinational Verification Techniques ,
in Proceedings of the International Conference on Computer Design, October 1997, Austin, TX
Reachability Analysis Using Partitioned-ROBDDs,
in Proceedings of the International Conference on Computer Aided Design, Nov. 1997, San Jose, CA.
Logic Synthesis for Large Pass Transistor Circuits,
in Proceedings of the International Conference on Computer Aided Design, Nov. 1997, San Jose, CA.
Design Validation Techniques: A Tutorial,
One day tutorial at the 11th International Conference on VLSI Design, Jan. 1998,
Madras, India.
Wireplanning in Logic Synthesis ,
in Proceedings of the ACM/IEEE International Workshop on Logic Synthesis, May 1998, Tahoe City, CA
Functional Validation Techniques: A Tutorial,
One day tutorial at the 35th Design Automation Conference, June, 1998, San Francisco, CA. (to appear)
Back to Amit's Home Page