Functional Validation Techniques: A Tutorial
Abstract
The increasing complexity of VLSI systems has made
their functional validation extremely difficult. Indeed,
verification has become the bottleneck in the IC
design process today, with validation teams often being comparable
in size to design teams.
This tutorial covers state-of-the-art validation techniques.
These include the traditional methods of
simulation and emulation, as well as the emerging formal
verification technologies.
We will summarize many of the university
and commercial CAD tools that incorporate these ideas.
Specifically, the tutorial will cover the following
topics:
Computational models for designs
State-of-the-art simulation techniques
Emulation technology
Formal equivalence of combinational and sequential
gate and RTL level designs
Formal property verification using model checking,
language containment, symbolic trajectory evaluation and theorem proving
Techniques for advancing the frontiers of verification
ranging from approximation techniques to combining formal verification with simulation for better coverage
Theory will be
reinforced by practice through the use of software demonstrations of
public domain tools. Emphasis will be placed on techniques
which can handle large scale designs.
The tutorial will be of interest to the following audience:
Digital designers and design project managers:
In understanding and choosing validation techniques that are best
suited for different design stages. This will assist evaluation of
commercial validation offerings, and help devise a comprehensive
validation strategy in which bugs are caught early in the design
cycle.
CAD vendors:
In identifying technologies that are
relatively mature in the research community and are ready to be
commercialized.
Researchers:
In identifying open research problems,
where significant advances can be made.
What distinguishes this tutorial from previous ones is that it
provides a survey of methods for functional
validation, rather than focus on a particular technology alone.
For comments contact
anarayan@ic.eecs.berkeley.edu