Incremental Block-Level Silicon Compilation Methodology for Deep Sub-micron ASICs: An Object-Oriented Approach

Abdallah Tabbara

Objective

It is generally agreed within the EDA community [5] that Deep Sub-Micron (DSM) semiconductor technology is forcing major discontinuities in traditional design methods. The complexity and scale of integration, as well as the significant cost of design errors, promotes a re-evaluation of design practice and an increase in "co-design" early in the design process.

In this work, we lay the groundwork for a new design system that exploits both a recently proposed methodology [1] for performing logic and physical design in parallel [4], and object-oriented modeling schemes for design specification. The method allows for incremental design exploration and refinement at all levels of abstraction and permits the rapid characterization of the final placed and routed design block by block, and object by object.

Block Oriented Methodology

The block oriented methodology [1] offers a significant advantage over current approaches:

• does not distinguish between the "front" and "back" end (i.e. allows vertical integration)
• allows complete functional and post-layout timing verification of each block
• provides physical design information early in the design cycle
• permits engineering changes by refinement at any time in the design flow
• has a smaller margin of error (and potential re-design, and re-allocation of area, and timing slacks) in layout because of localized constraint handling

This method removes the need for pre-layout and post-layout gate level simulations and the full chip level iteration between the front and back ends, and preserves the hierarchy and structure of the design; information that is quite valuable and most often glossed over in typical design tools.

Object-Oriented Specification

Most current design practices tend to focus on functionality in all but the lowest abstraction levels. Specification, and synthesis decompose the design based on functional hierarchy, and neglect structure. Interface, communication, and structural dependencies among blocks in the design are only addressed during the physical design stage, after the RT level description is generated.

The object-oriented decomposition approach, is only now being recognized as a formal model of specification from which a hardware system can ultimately be developed [10]. Objects can represent both structure and function, and thus provide a more powerful means of specification for system blocks and hierarchy by means of instantiation, encapsulation, and methods for communication.

In this effort, we use elements of OMT [6] to define a suitable subset of Java for design entry and specification, and then "silicon-compile" these object blocks into a structural implementation.

Progress and Status

We have been able to lay the groundwork for implementing a block level object-oriented silicon compiler [2] that takes as input Java code [8], extracts the object decomposition, and generates a structural layout at the gate level, that can be debugged visually just like software code to allow for rapid iteration between the front and back ends.

The major thrust of this work is directed at addressing the specification of the "silicon-code" in an OO fashion, and defining guidelines for design entry instead of putting restrictions on the language. The guidelines serve to unambiguously interpret the specification into a format that can be implemented in both hardware and software in an unbiased fashion. We specify a subset of Java and a policy for specification in order to ensure that hardware (logic and latches) can be properly inferred from the specification. We attempted to be as flexible as possible in order to ensure that objects can also be implemented in software thus exploiting Java's potential as a description language for embedded systems [9].

We developed a tool that extracts objects from the Java specification [8], and generates the Class File Intermediate Format (CFIF) which contains all the information needed by the silicon compiler for both front and back annotation.

Future Work

This project will serve as a proof of concept for the object-oriented block level silicon compilation approach, and will help us refine our ideas into a more general scheme and system that can handle a larger subset of the input language if needed, and potentially interface to commercial CAD tools [7]. We hope to get feedback from designers in academia and industry and evaluate the potential of this approach. We hope that with positive feedback we can implement our full vision as described earlier.

References

1. Eory, F. "Systems to Silicon Design: Methodology for Deep Sub-micron ASICs", SuperCon, 1997
2. Mead, C. et. al. "Introduction to VLSI systems" Addison-Wesley, 1980
3. McLeod, J. "Silicon Compilation Strikes a Chord", Integrated Systems and Design Magazine, 1997
4. Newton, A. R. Personal Communication, 1997
5. "National Technology Roadmap for Semiconductors", Semiconductor Industry Association, 4300 Stevens Creek Blvd., Suite 271, San Jose, CA 95129, phone: (408) 246-2711.
6. Rumbaugh, J. "Object-Oriented Modeling and Design" Prentice Hall, 1991
7. Sentovich, E. M. et. al. "Sequential Circuit Design Using Synthesis and Optimizations" ICCAD, 1992
8. Sun Mircosystems, Inc. "Java Virtual Machine Specification", 1997
9. Young, J. S. Tabbara, A. et. al. "Design and Specification of Embedded Systems through Successive Formal Refinement of Java Programs" submitted to DAC, 1998
10. Zhou, X. "Building Blocks and their Interactions" IEEE Potentials Magazine, October 1997

Please send comments to: Abdallah Tabbara (atabbara@ic.eecs.berkeley.edu)