Incremental Block-Level Silicon Compilation Methodology for Deep Sub-micron: A Component-Based Approach

Abdallah Tabbara

It is generally agreed within the EDA community [5] that Deep Sub-Micron (DSM) semiconductor technology is forcing major discontinuities in traditional design methods. The complexity and scale of integration, as well as the significant cost of design errors, promotes a re-evaluation of design practice and an increase in "co-design" early in the design process.

In this work, we lay the groundwork for a new design system that exploits both a recently proposed methodology [1] for performing logic and physical design in parallel [4] in a non-iterative fashion [11], using object-oriented modeling and component based schemes for design specification. The method allows for incremental design exploration and refinement at all levels of abstraction and permits the rapid characterization of the final placed and routed design block by block, and object by object. For a more detailed description of the methodology the reader is referred to the following discussion.

We have been able to lay the groundwork for implementing a block level component-based silicon compiler [2]. It takes as input Java code [8], extracts the object decomposition, and generates a structural layout at the gate level, that can be debugged visually just like software code to allow for rapid iteration between the front and back ends.

More recent efforts have been directed towards accomplishing two goals. First, in order to better understand the issues involved in the new design methodologies being suggested [11], we studied the problem of retiming with area delay trade-offs and delay constraints in a new non-iterative approach [11]. Initial results show that a reinterpretation of classical algorithms to solve this problem is needed. The resulting algorithms will be included in the tool, which is being developed. A paper describing this work has been submitted to DAC.

On the other hand, work has been initiated towards completing and updating the non-iterative flow for DSM, suggested in [11]. This involved working on a routing driven placement methodology that complements that flow. Its main characteristics are:

• path-based approach
• timing is first-class object
• mathematical engine at path level to solve general questions
• iterative improvement placement algorithm augmented with fast, complete routing heuristics in the placement loop
• incremental: capability for
• incremental restart
• handling partial solution
• handles issues of retiming
• handling big number of modules: hard, firm and soft blocks

The ultimate goal of this work is to develop a tool that has an impact in DSM by supporting reuse, where IP blocks that have timing constraint have to be combined to result in a certain functionality.

This project will serve as a proof of concept for the component-based block-level silicon compilation approach. It will help us refine our ideas into a more general scheme and system that can handle a larger subset of the input language if needed, and potentially interface to commercial CAD tools [7].

A more detailed list of milestones includes:

• Working on a routing driven placement flow that will complement the flow suggested in [11]
• Working on solving other algorithmic problems suggested by the new flow [11]

1. Eory, F. "Systems to Silicon Design: Methodology for Deep Sub-micron ASICs", SuperCon, 1997
2. Mead, C. et. al. "Introduction to VLSI systems" Addison-Wesley, 1980
3. McLeod, J. "Silicon Compilation Strikes a Chord", Integrated Systems and Design Magazine, 1997
4. Newton, A. R. Personal Communication, 1997
5. "National Technology Roadmap for Semiconductors", Semiconductor Industry Association, 4300 Stevens Creek Blvd., Suite 271, San Jose, CA 95129, phone: (408) 246-2711
6. Rumbaugh, J. "Object-Oriented Modeling and Design" Prentice Hall, 1991
7. Sentovich, E. M. et. al. "Sequential Circuit Design Using Synthesis and Optimizations" ICCAD, 1992
8. Sun Mircosystems, Inc. "Java Virtual Machine Specification", 1997
9. Young, J. S. Tabbara, A. Newton, A. R. et. al. "Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement" DAC, 1998
10. Zhou, X. "Building Blocks and their Interactions" IEEE Potentials Magazine, October 1997
11. Otten, R.H.J.M. Brayton, R.K. "Planning for Performance" DAC, 1998

Please send comments to: Abdallah Tabbara (atabbara@ic.eecs.berkeley.edu)