Abdallah Tabbara, Graduate Student
(Professor Robert K. Brayton) (Professor A. Richard Newton)
Funding Sources: GSRC, SRC contract 98-DC-324, California MICRO Program,
The rapid scaling of IC technology leads to smaller devices, closer interconnects and higher degrees of on chip integration, which requires a stronger interaction between the high level synthesis and the low level physical design. Based on the idea of planning for performance[1], a new DSM design methodology has been proposed, where retiming explores the area delay tradeoffs at a floor planning level, combining synthesis and physical design and minimizing the number of iterations needed. Within this design flow, this work (a) integrates module placement and routing with the same data structure, (b) searches a feasible place/route solution satisfying the constraints prescribed by retiming, and (c) incrementally changes the solution within a reasonable number of iterations. Optimization algorithms and schemes will be explored to be scalable and capable for the problem.
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