For this application, we chose an industrial design from Motorola. This circuit acts as the controller between a CPU and a serial bus. Input designs of different sizes were created by replicating the number of controllers in the design. The performance ratios are shown in Figure 2. We notice that 1) relative performance of various machines remain unchanged with increase in the input size, and 2) performance of the machines is proportional to the clock rate. These observations substantiate our hypothesis that the computations in the hardware compiler are very local and the performance is dominated by the clock speed of the machine with little or no effect from memory organization.