Publiations

• Compilation, Synthesis, and Simulation of Hardware Description Languages -- The Compositional Models of HDL's, by Szu-Tsung Cheng, PhD thesis, University of California, Berkeley, 1998.
• Finite State Machine Communicaiton in V++, by Szu-Tsung Cheng, PatrickC. McGeer, Tom Truman, Patrick Scaglia, Alberto Sangiovanni-Vincentelli, Robert K. Brayton, in Cadence Technical Conference, 1998.
• Object-Oriented Simulation of Hardware Descriptions: Solving the Namespace Problem in a Pure Hardware Language, by Szu-Tsung Cheng, Patrick C. McGeer, Fabio Somanzi, Patrick Scaglia, in Cadence Technical Conference, 1998.
• The V++ System Design Language, by Szu-Tsung Cheng, Patrick C. McGeer, Mike Meyer, Tom Truman, Alberto Sangiovanni-Vincentelli, Patrick Scaglia, in Design Automation and Test in Europe, 1998.
• The Synchronous Semantics of Verilog: A Functional Interpretation of Verilog Programs, by Szu-Tsung Cheng, Alexander Saldanha, Patrick C. McGeer, Patrick Scaglia, Robert K. Brayton, Cadence Technical Conference, 1997.
• The V++ System Design Language, by Szu-Tsung Cheng, Patrick C. McGeer, Mike Meyer, Alberto Sangiovanni-Vincentelli, Patrick Scaglia, Internation Workshop on Logic Synthesis, 1997.
• Synthesizing Multi-Phase HDL Programs, by Szu-Tsung Cheng, Robert K. Brayton, in the Proceedings of Internation Verilog Conference, 1996.
• Cycle Simulatioin Semantics of Verilog and SMV: Cobra from Concept to Simulator, by Szu-Tsung Cheng, Patrick C. McGeer, Kennith L. McMillan, Alexander Saldanha, Alberto Sangiovanni-Vincentelli, Patrick Scaglia, in Cadence Technical Conference, 1996.
• VIS: A System for Verification and Synthesis, by Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa, in the Proceedings of the Conference on Computer Aided Verification, New Brunswich, MJ, July, 1996.
• VIS, by Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, in FMCAD'96.
• HSIS: A BDD-Based Environment for Formal Verification", by Adnan Azia, Felice Balarin, Szu-Tsung Cheng, Ramin Jojati, Timothy Kam, S. C. Krishnan, Rajeev K. Ranjan, Thomas Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, in 31st ACM/IEEE Design Automation Conference.
• Parallelism and Locality in Priority Queues, by A. Ranade, S.-T. Cheng, E. Deprit, J. Jones, S.-I. Shih, in the Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, Dallas, October 26-29, 1994.
• Formal Design Verification of Digital Systems, by Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, T. Kam, S. C. Krishnan, Thomas R. Shiple, Vigyan Singhal, Huey-Yih Wang, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, in SRC Techon'93.
• Szu-Tsung Cheng's Master Thesis: Compiling Verilog into Automata
• A Medthodology for Formal Verification of Real-Time Systems, ERL Memo M95/11, by F. Balarin, R. K. Brayton, S.-T. Cheng, D. A. Kirkpatrick, A. Sangiovanni-Vincentelli
• Compiling Verilog into Timed Finite State Machines, IVC'95, by Szu-Tsung Cheng, Robert K. Brayton, Gary York, Katherine A. Yelick, Alexander Saldanha
• A Neural Network Simulating System, by Ja-Ling Wu, Szu-Tsung Cheng, in The Computer Journal, vol. 34, No. 1, 1991.