Feature Articles

For Sale: Intellectual Property
By Melanie Fox

Analogous to building highrises that concentrate services for limited-space urban settings, electronics manufacturers are producing system ICs that incorporate the functionality of CPUs, decoders, memory, graphics processors, and other core designs. The highly-integrated ICs save PC board real estate and help decrease product costs. But, high-level integration magnifies design complexity and introduces new collaborative issues as IC providers share their valuable - and traditionally proprietary - intellectual property for integration by other departments or outside firms. Industry leaders are cooperating to define enabling standards and to deliver advanced design and simulation tools that support integrating many suppliers functions on a single chip.

The Benefits of Silicon-Level Integration
Semiconductor processing technology advances at an almost unbelievable rate. Each new chip generation integrates more functionality, delivers higher performance and higher reliability, requires less power, and costs less to manufacture. With fabrication technology that can incorporate millions of gates into a single piece of silicon, one chip can now do the work of multiple earlier-generation ICs. This new level of integration is shifting IC focus from the PC board level to the silicon level. Much like physical components are incorporated onto a printed circuit board, ICs are now being incorporated into multifunction system chips.
Driven by large potential economic wins, companies are quickly moving to incorporate the super-integrated ICs into a range of products. Consumer products such as PCs, set-top boxes, and cell phones promise the best economies of scale. Advantages include expanded product functionality, decreased physical size, and the lowering of prices to levels that are acceptable to much larger segments of the consumer markets. Consider cell phones, previously requiring dozens of chips, but now produced with only two or three ICs. Taking advantage of the highly-integrated chip technology, the new phones offer more affordable features and boast a longer battery life than earlier versions — with overall size no bigger than a card deck.

The Issues
But integration of intellectual property (IP) does not come simply. The challenges faced by designers and manufacturers include both technical and business-related issues.

Complexity
Using high-level IP integration, designers no longer start at the lowest levels of gate and Boolean function layout. Instead they are putting down 100,000-gate pre-defined functions such as MPEG decoders. Detailed fabrication data is required to effectively integrate functionality and to interface components. The complexity can be overwhelming — as the IC design gets larger, it becomes increasingly difficult to comprehend. Simulation times also increase as more functionality is integrated.

Multiple IP Sources
The new ICs can integrate functionality from dozens of independent semiconductor design teams, and even outside sources. Implemented in a wide variety of formats, IP blocks from different organizations introduce inherent incompatibilities.

Security
To design and build around the IC blocks, detailed implementation data must be supplied by the IP originators. But, simultaneous with sharing detailed design data, providers must protect their IP and avoid irresponsible or illegal use of it. Legal contracts and audit processes do not offer adequate deterrents.

Shrinking Market Windows
To be able to start the product design phase with sophisticated, re-usable IC building blocks represents a major improvement. Even so, consumer product obsolescence cycles are typically less than one year. PCs, for example, have a 7-month obsolescence cycle. A huge gap still exists between what can be designed and what can be fabricated within the narrow market windows. Extremely complex, super-IC designs must be integrated and tested in only months.

New Developments Address the Issues
Industry cooperation and joint product development projects promise progress.

Multiple IP Delivery Methods
Providers are tailoring IP deliverables to the specific customer requirements, offering only the components necessary to the customer's design task. IP blocks are typically available in one of three forms:

Soft View. Design data comprises a synthesizable register-transfer-level (RTL) description. This form of IP is flexible but requires the customer to go through some times time-consuming synthesis process.

Firm View. Data includes the RTL description plus physical placement data. Firm IP can be flexible and more productive than soft since it is already in an implemented form.

Hard View. Actual layout is provided, in some cases expressed in GDS II format that can be used for photolithography mask generation. Hard is the least flexible, but it fully implemented and verified.

IP deliverables range from a functional description of the design, to a manufacturing description of design, or a level of source that can be converted by the user to a manufacturable design. Components can include support software, verification suites and methodology (with test vectors supplied for simulation), various levels of simulation models to validate the design, or even the whole collection of archived design data. Deliverables decisions are made on a case-by-case basis, with consideration given to both the project requirements and the integrity of the relationship between the cooperating organizations.
Many companies are turning to third-party relationships for improving IP security when dealing with an outside source or client. For example, both an IP provider and the client can deliver designs and specifications to a trusted third party for manufacture. Standardized business contracts help to outline important security precautions and considerations, and audit trails and digital watermarks are being implemented to further protect IP.

Standards Definition
Almost 100 electronics firms, including companies like Cadence Design Systems, Inc., Silicon Graphics, Inc., Sony Corporation, Synopsys, Inc., Toshiba Corporation, Viewlogic Systems, Inc., and VLSI Technology, Inc., have united to form the Virtual Socket Interface (VSI) Alliance. The membership represents corporate design groups, semiconductor vendors, electronic design automation (EDA) vendors, and independent IP providers, and shares the goals of enabling and promoting IP design integration.
Alliance members are working to unify the industry's system-chip vision, and to define technical standards needed to mix and match IP blocks from multiple sources. Early plans include development of a baseline proposal (the Virtual Socket Interface) that establishes common interface standards, allowing virtual components to fit into "virtual sockets" at both the functional and physical levels.
The Open Modeling Forum (OMF), including Cadence, IKOS Systems, Inc., and Intel, is also developing guidelines for the delivery of IP simulation models. The group reviews mechanisms for securing and delivering object code models, as well as full source code models, to applications that require them. Plans include distributing secure evaluation models through the World Wide Web. Customers will evaluate IP models — even review designs based on them — using these models before having to make a purchase commitment.

Software Co-validation
Huge productivity gains can be realized if software is verified in conjunction with system hardware. But with significant amounts of software to validate, the process has typically been prohibitively slow. New hardware modeling methods allow the use of the actual ICs during simulation, thereby greatly streamlining the verification process.

Predictable and Pre-verified IPs
System-level verification demands full confidence in the functionality and behavior of each of the building blocks. Pre-verified IPs simplify the testing efforts and reduce simulation time.
The availability of powerful IPs provides major new commercial opportunities. Although the design of system-level chips can be extremely complex, new tools and industry standards are helping to simplify collaborative efforts and to proliferate the use of super-integrated ICs.

Melanie Fox is a freelance writer and marketing consultant working out of Waldo, Maine.

The Benefits of Silicon-Level Integration

The Issues

Complexity

Multiple IP Sources

Security

Shrinking Market Windows

New Developments Address the Issues

Multiple IP Delivery Methods

Standards Definition

Software Co-validation

Predictable and Pre-verified IPs

Cover Page | Feature Articles | Software and Services | Table of Contents | Search

Copyright 1997. Cadence Design Systems, Inc. Corporate Marketing

	Analogous to building highrises that concentrate services for limited-space urban settings, electronics manufacturers are producing system ICs that incorporate the functionality of CPUs, decoders, memory, graphics processors, and other core designs. The highly-integrated ICs save PC board real estate and help decrease product costs. But, high-level integration magnifies design complexity and introduces new collaborative issues as IC providers share their valuable - and traditionally proprietary - intellectual property for integration by other departments or outside firms. Industry leaders are cooperating to define enabling standards and to deliver advanced design and simulation tools that support integrating many suppliers functions on a single chip.
The Benefits of Silicon-Level Integration	Semiconductor processing technology advances at an almost unbelievable rate. Each new chip generation integrates more functionality, delivers higher performance and higher reliability, requires less power, and costs less to manufacture. With fabrication technology that can incorporate millions of gates into a single piece of silicon, one chip can now do the work of multiple earlier-generation ICs. This new level of integration is shifting IC focus from the PC board level to the silicon level. Much like physical components are incorporated onto a printed circuit board, ICs are now being incorporated into multifunction system chips. Driven by large potential economic wins, companies are quickly moving to incorporate the super-integrated ICs into a range of products. Consumer products such as PCs, set-top boxes, and cell phones promise the best economies of scale. Advantages include expanded product functionality, decreased physical size, and the lowering of prices to levels that are acceptable to much larger segments of the consumer markets. Consider cell phones, previously requiring dozens of chips, but now produced with only two or three ICs. Taking advantage of the highly-integrated chip technology, the new phones offer more affordable features and boast a longer battery life than earlier versions — with overall size no bigger than a card deck.
The Issues	But integration of intellectual property (IP) does not come simply. The challenges faced by designers and manufacturers include both technical and business-related issues.
Complexity	Using high-level IP integration, designers no longer start at the lowest levels of gate and Boolean function layout. Instead they are putting down 100,000-gate pre-defined functions such as MPEG decoders. Detailed fabrication data is required to effectively integrate functionality and to interface components. The complexity can be overwhelming — as the IC design gets larger, it becomes increasingly difficult to comprehend. Simulation times also increase as more functionality is integrated.
Multiple IP Sources	The new ICs can integrate functionality from dozens of independent semiconductor design teams, and even outside sources. Implemented in a wide variety of formats, IP blocks from different organizations introduce inherent incompatibilities.
Security	To design and build around the IC blocks, detailed implementation data must be supplied by the IP originators. But, simultaneous with sharing detailed design data, providers must protect their IP and avoid irresponsible or illegal use of it. Legal contracts and audit processes do not offer adequate deterrents.
Shrinking Market Windows	To be able to start the product design phase with sophisticated, re-usable IC building blocks represents a major improvement. Even so, consumer product obsolescence cycles are typically less than one year. PCs, for example, have a 7-month obsolescence cycle. A huge gap still exists between what can be designed and what can be fabricated within the narrow market windows. Extremely complex, super-IC designs must be integrated and tested in only months.
New Developments Address the Issues	Industry cooperation and joint product development projects promise progress.
Multiple IP Delivery Methods	Providers are tailoring IP deliverables to the specific customer requirements, offering only the components necessary to the customer's design task. IP blocks are typically available in one of three forms: Soft View. Design data comprises a synthesizable register-transfer-level (RTL) description. This form of IP is flexible but requires the customer to go through some times time-consuming synthesis process. Firm View. Data includes the RTL description plus physical placement data. Firm IP can be flexible and more productive than soft since it is already in an implemented form. Hard View. Actual layout is provided, in some cases expressed in GDS II format that can be used for photolithography mask generation. Hard is the least flexible, but it fully implemented and verified. IP deliverables range from a functional description of the design, to a manufacturing description of design, or a level of source that can be converted by the user to a manufacturable design. Components can include support software, verification suites and methodology (with test vectors supplied for simulation), various levels of simulation models to validate the design, or even the whole collection of archived design data. Deliverables decisions are made on a case-by-case basis, with consideration given to both the project requirements and the integrity of the relationship between the cooperating organizations. Many companies are turning to third-party relationships for improving IP security when dealing with an outside source or client. For example, both an IP provider and the client can deliver designs and specifications to a trusted third party for manufacture. Standardized business contracts help to outline important security precautions and considerations, and audit trails and digital watermarks are being implemented to further protect IP.
Standards Definition	Almost 100 electronics firms, including companies like Cadence Design Systems, Inc., Silicon Graphics, Inc., Sony Corporation, Synopsys, Inc., Toshiba Corporation, Viewlogic Systems, Inc., and VLSI Technology, Inc., have united to form the Virtual Socket Interface (VSI) Alliance. The membership represents corporate design groups, semiconductor vendors, electronic design automation (EDA) vendors, and independent IP providers, and shares the goals of enabling and promoting IP design integration. Alliance members are working to unify the industry's system-chip vision, and to define technical standards needed to mix and match IP blocks from multiple sources. Early plans include development of a baseline proposal (the Virtual Socket Interface) that establishes common interface standards, allowing virtual components to fit into "virtual sockets" at both the functional and physical levels. The Open Modeling Forum (OMF), including Cadence, IKOS Systems, Inc., and Intel, is also developing guidelines for the delivery of IP simulation models. The group reviews mechanisms for securing and delivering object code models, as well as full source code models, to applications that require them. Plans include distributing secure evaluation models through the World Wide Web. Customers will evaluate IP models — even review designs based on them — using these models before having to make a purchase commitment.
Software Co-validation	Huge productivity gains can be realized if software is verified in conjunction with system hardware. But with significant amounts of software to validate, the process has typically been prohibitively slow. New hardware modeling methods allow the use of the actual ICs during simulation, thereby greatly streamlining the verification process.
Predictable and Pre-verified IPs	System-level verification demands full confidence in the functionality and behavior of each of the building blocks. Pre-verified IPs simplify the testing efforts and reduce simulation time. The availability of powerful IPs provides major new commercial opportunities. Although the design of system-level chips can be extremely complex, new tools and industry standards are helping to simplify collaborative efforts and to proliferate the use of super-integrated ICs.