CS250 Homework 2
This is our explanatory notes for the second part of homework 2 and we implemented the "reg file" part.
Bank 3 bits
RS1 6 bits
RS2 6 bits
R/W' 1 bits
Mode 1 bits
Mask 2 bits
So these fields line up as follows:
Bank RS1 RS2 R/W' Mode Mask --> total 19 bits long
Each control word is equal in length. We also need control word for Write A and Write B, we decide to make all the control work equal in length.
At cycle 0, we do 2 writes
the input vector , with each of the data field indicated below, is:
(enable) _(data for Bus A)_(data for Bus B)_(cw for W at bus A)_(cw for W at bus B)_(cw for R)
0_00000000DEADBEEF_AAAAAAAAAAAABBBB_00003_7E003_00000
the outputs are:
0, in1 = 00000000deadbeef, in2 = aaaaaaaaaaaabbbb, out = xxxxxxxxxxxxxxxx
At cycle 1, we do a read
0_0000000000000000 _ 0000000000000000_00008_00008_0000B
the outputs are:
1, in1 = 0000000000000000, in2 = 0000000000000000, out = 00000000deadbeef
(we read out what got written into the mem for bus A(64 bits) last cycle)
At cycle 2, we do one read
0_0000000000000000_0000000000000000_00008_00008_7E00B
the outputs are:
2, in1 = 0000000000000000, in2 = 0000000000000000, out = aaaaaaaaaaaabbbb
( we read out what got written into the mem for bus B(64 bits) @ cycle 0)
At cycle 3, we do 1 write
0_0000000000000011_0000000000000000_0FC01_00008_00000
the outputs are:
3, in1 = 0000000000000011, in2 = 0000000000000000, out = aaaaaaaaaaaabbbb
We read nothing, so the output value unchanged, 11 is written into mem at the end of the bank
At cycle 4, we did one read to verify the read wraps within bank 0
0_0000000000000000_0000000000000000_00008_00008_0FC0B
the outputs are:
4, in1 = 0000000000000000, in2 = 0000000000000000, out = 000000deadbeef11
( Mem content from diferent row is read and wrapped around (same bank only) )
At cycle 5, we did 1 write to the second row of the bank
0_00000000FEEDBEEF_0000000000000000_02002_00008_00000
the outputs are:
5, in1 = 00000000feedbeef, in2 = 0000000000000000, out = 000000deadbeef11
( We write in "feedbeef" for the next cycle)
At cycle 6, we did 2 32 bit read both from same bank
0_0000000000000000_0000000000000000_00008_00008_0008E
the outputs are:
6, in1 = 0000000000000000, in2 = 0000000000000000, out = feedbeefdeadbeef (we read out 2 32bits from two different row of the same bank)
At cycle 7, read write disabled
1_0000000000000000_0000000000000000_00000_00000_0000B
Source code implementation are available below:
bank.v column.v reg.v toplevel.v barrel.v test_top.v
4/11/97