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June 08, 2010, at 10:06 AM by Edward A. Lee -

Changed line 3 from:

# (8/27) ~~Discussion~~

to:

# (8/27) Discussion: Course introduction and logistics.

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# (9/3) ~~Discussion~~

to:

# (9/3) Discussion: [CXH or JR] Version control (SVN)

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# (9/8)
~~# (9/10) Discussion~~

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# (9/8) [JR away]
# (9/10) Discussion [JR away]

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# (10/13)
~~# (10/15) Discussion~~

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# (10/13) [SS away]
# (10/15) Discussion [SS away]

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# (11/8)
# (11/10)

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# (11/8) [SS and JR away, tentatively]
# (11/10) [SS and JR away, tentatively]

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** Introduction to computer-aided design methodologies (RTL, TLM, Analog, CPS)

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** Introduction to computer-aided design methodologies (e.g. Register-Transfer-Level: RTL, Transaction-level modeling: TLM)
** Analog CAD, cyber-physical systems

Added lines 79-92:

# Software Engineering (consult Andreas)
** Version control: SVN
** Eclipse
** Working with open-source code
** Copyrights and licenses
** Language features: templates, operator overloading
** When to use what language
** Building on Ptolemy II

!! Suggested Projects

# Scheduling dataflow graphs for minimum memory usage.
# Scheduling dataflow graphs on parallel processors.

June 08, 2010, at 09:42 AM by Edward A. Lee -

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# (8/27) Discussion
# (8/30)
# (9/1)
# (9/3) Discussion
# (9/6) Holiday
# (9/8)
# (9/10) Discussion
# (9/13)
# (9/15)
# (9/17) Discussion
# (9/20)
# (9/22)
# (9/24) Discussion
# (9/27)
# (9/29) [MuSyC review]
# (10/1) Discussion
# (10/4) [EAL away]
# (10/6) [EAL away]
# (10/8) Discussion [EAL away]
# (10/11)
# (10/13)
# (10/15) Discussion
# (10/18)
# (10/20)
# (10/22) Discussion
# (10/25) [ESWeek, EAL away]
# (10/27) [ESWeek, EAL away]
# (10/29) Discussion [ESWeek, EAL away]
# (11/1)
# (11/3)
# (11/5) Discussion
# (11/8)
# (11/10)
# (11/12) Discussion
# (11/15)
# (11/17)
# (11/19) Discussion
# (11/22)
# (11/24)
# (11/26) Holiday: Thanksgiving
# (11/29)
# (12/1)
# (12/3) Discussion: Last day of instruction

!! Topics

Deleted line 49:

** Introduction to computer-aided design methodologies (e.g. Register-Transfer-Level: RTL, Transaction-level modeling: TLM)

Added lines 51-52:

** Introduction to computer-aided design methodologies (e.g. Register-Transfer-Level: RTL, Transaction-level modeling: TLM)
** Analog CAD, cyber-physical systems

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Deleted lines 77-78:

June 08, 2010, at 09:30 AM by Edward A. Lee -

Changed lines 3-14 from:

# Modeling, problem formulation, abstraction/refinement, nondeterminism, discrete vs. continuous.
# Modeling continuous systems 1.
# Modeling continuous systems 2.
# Boolean modeling: True (feasible) vs. False (infeasible) paths. Basic Boolean algebra: cube, minterm, Boolean operations, factorization, etc.
# Solving SAT problems.
# BDDs
# Logic synthesis and optimization
# Reachability analysis and temporal logic: model checking
# Parallel programming for dynamic programming and graph algorithms.
#
# Emerging problem spaces: Biosystems, cyber-physical systems, nanotechnology

to:

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to:

** Modeling, problem formulation, abstraction/refinement, nondeterminism, discrete vs. continuous.

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* Algorithms ~~for Continuous Models~~
- Solving nonlinear equations (e.g. Newton-Raphson)
- Solving continuous-time dynamics numerically (transient concepts)
- Continuous-time frequency domain concepts and computational algorithms
~~- Continuous-time stochastics~~

* From Algorithms to Software
- Complexity and modularity
- Concurrency and parallelism

to:

# From Algorithms to Software
** Complexity and modularity
** Concurrency and parallelism
** Parallel programming for dynamic programming and graph algorithms.

# Algorithms for Continuous Models

** Solving nonlinear equations (e.g. Newton-Raphson)
** Solving continuous-time dynamics numerically (transient concepts)
** Continuous-time frequency domain concepts and computational algorithms
** Continuous-time stochastics

# Emerging problem spaces: Biosystems, cyber-physical systems, nanotechnology

June 08, 2010, at 09:27 AM by Edward A. Lee -

Deleted lines 2-3:

# Intro problem space (CAD (RTL, TLM), software, circuits).
# Longest/shortest path in a DAG. Timing analysis for circuits and embedded software.

Changed lines 21-43 from:

   ~~- Timing analysis for circuits and embedded software~~
      ~~. True (feasible) vs. False~~ (infeasible) paths
+ Hash functions
- Discrete-event simulations (e.g. in calendar queue for maintaining an
~~event queue)~~
- other applications?
+ Linear programming and ILP
~~[several applications -- which ones to cover?]~~
~~+ Observability~~ and ~~controllability~~
~~- Testing for stuck-at & delay faults~~
- Controller synthesis ?
+ Basic Boolean algebra: cube, minterm, Boolean operations, factorization, etc.
   - Logic synthesis and optimization
+ Boolean function representation & manipulation (BDDs)
- Equivalence checking, model checking, etc.
+ Boolean satisfiability (SAT)
- Equivalence checking of combinational circuits (aka "implementation verification")
+ Reachability analysis & temporal logic
- Formal verification: Sequential equivalence checking, model checking
+ Scheduling algorithms
- dataflow models, managing event queues
- other applications?

to:

** Timing analysis for circuits and embedded software (common themes: True (feasible) vs. False (infeasible) paths)
** Hash functions (e.g. in Discrete-event simulations, use of a calendar queue for maintaining an event queue)
** Linear programming and ILP [several applications -- which ones to cover?]
** Observability and controllability (Testing for stuck-at & delay faults, Controller synthesis?)
** Basic Boolean algebra: cube, minterm, Boolean operations, factorization, etc. (Logic synthesis and optimization)
** Boolean function representation & manipulation (BDDs): Equivalence checking, model checking, etc.
** Boolean satisfiability (SAT): Equivalence checking of combinational circuits (aka "implementation verification")
** Reachability analysis & temporal logic: Formal verification: Sequential equivalence checking, model checking
** Scheduling algorithms: dataflow models, managing event queues, parallel scheduling (multicore, high-level circuit synthesis).

June 08, 2010, at 09:22 AM by Edward A. Lee -

Changed lines 17-22 from:

* Introduction:
- Introduction to computer-aided design methodologies (e.g. Register-Transfer-Level: RTL, Transaction-level modeling: TLM)
- Examples of problem domains: integrated circuits, biosystems, nanosystems, smart buildings, etc.

* Algorithms for Discrete Models (with their applications)
+ Longest/shortest path in a DAG

to:

# Introduction:
** Introduction to computer-aided design methodologies (e.g. Register-Transfer-Level: RTL, Transaction-level modeling: TLM)
** Examples of problem domains: integrated circuits, biosystems, nanosystems, smart buildings, etc.

# Algorithms for Discrete Models (with their applications)
** Longest/shortest path in a DAG

June 08, 2010, at 09:21 AM by Edward A. Lee -

Added lines 17-56:

* Introduction:
- Introduction to computer-aided design methodologies (e.g. Register-Transfer-Level: RTL, Transaction-level modeling: TLM)
- Examples of problem domains: integrated circuits, biosystems, nanosystems, smart buildings, etc.

* Algorithms for Discrete Models (with their applications)
+ Longest/shortest path in a DAG
- Timing analysis for circuits and embedded software
. True (feasible) vs. False (infeasible) paths
+ Hash functions
- Discrete-event simulations (e.g. in calendar queue for maintaining an
event queue)
- other applications?
+ Linear programming and ILP
[several applications -- which ones to cover?]
+ Observability and controllability
- Testing for stuck-at & delay faults
- Controller synthesis ?
+ Basic Boolean algebra: cube, minterm, Boolean operations, factorization, etc.
- Logic synthesis and optimization
+ Boolean function representation & manipulation (BDDs)
- Equivalence checking, model checking, etc.
+ Boolean satisfiability (SAT)
- Equivalence checking of combinational circuits (aka "implementation verification")
+ Reachability analysis & temporal logic
- Formal verification: Sequential equivalence checking, model checking
+ Scheduling algorithms
- dataflow models, managing event queues
- other applications?

* Algorithms for Continuous Models
- Solving nonlinear equations (e.g. Newton-Raphson)
- Solving continuous-time dynamics numerically (transient concepts)
- Continuous-time frequency domain concepts and computational algorithms
- Continuous-time stochastics

* From Algorithms to Software
- Complexity and modularity
- Concurrency and parallelism

June 08, 2010, at 09:18 AM by Edward A. Lee -

Added line 13:

# Parallel programming for dynamic programming and graph algorithms.

May 11, 2010, at 10:04 PM by Edward A. Lee -

May 11, 2010, at 04:55 PM by Edward A. Lee -

Added line 12:

# Reachability analysis and temporal logic: model checking

May 11, 2010, at 04:52 PM by Edward A. Lee -

Changed lines 8-11 from:

# Boolean modeling: True (feasible) vs. False (infeasible) paths.

to:

# Boolean modeling: True (feasible) vs. False (infeasible) paths. Basic Boolean algebra: cube, minterm, Boolean operations, factorization, etc.
# Solving SAT problems.
# BDDs
# Logic synthesis and optimization

May 11, 2010, at 04:49 PM by Edward A. Lee -

Changed lines 4-5 from:

# Longest/shortest path in a DAG. Timing analysis for circuits and embedded software. ~~True (feasible) vs. False (infeasible) paths~~.
# Modeling~~, problem formulation, abstraction/refinement, nondeterminism~~.

to:

# Longest/shortest path in a DAG. Timing analysis for circuits and embedded software.
# Modeling, problem formulation, abstraction/refinement, nondeterminism, discrete vs. continuous.
# Modeling continuous systems 1.
# Modeling continuous systems 2.
# Boolean modeling: True (feasible) vs. False (infeasible) paths.

Changed lines 10-11 from:

# Emerging problem spaces: Biosystems, cyber-physical systems

to:

# Emerging problem spaces: Biosystems, cyber-physical systems, nanotechnology

May 11, 2010, at 04:45 PM by Edward A. Lee -

Changed line 3 from:

# Intro problem space (CAD (RTL, TLM), software~~, cyber-physical~~, circuits).

to:

# Intro problem space (CAD (RTL, TLM), software, circuits).

Changed lines 6-8 from:

to:

#
# Emerging problem spaces: Biosystems, cyber-physical systems

May 11, 2010, at 04:44 PM by Edward A. Lee -

Changed lines 3-5 from:

# Intro problem space
~~# Longest/shortest path in a DAG. Timing analysis for~~ circuits ~~and embedded software. True (feasible) vs~~. ~~False (infeasible)~~ paths

to:

# Intro problem space (CAD (RTL, TLM), software, cyber-physical, circuits).
# Longest/shortest path in a DAG. Timing analysis for circuits and embedded software. True (feasible) vs. False (infeasible) paths.
# Modeling, problem formulation, abstraction/refinement, nondeterminism.

May 11, 2010, at 04:43 PM by Edward A. Lee -

Changed lines 1-2 from:

~~Welcome to PmWiki~~!

to:

!! Lecture outline (Fall 2010, 27 lectures)

# Intro problem space
# Longest/shortest path in a DAG. Timing analysis for circuits and embedded software. True (feasible) vs. False (infeasible) paths

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