"EE298-7 --- VLSI CAD Seminar --- 1986-7" Sep 03 MODULE GENERATORS Glenn Adams - Topogate and Topogen Rick Mcgeer - Generating cells using Prolog Gino Cheng - A Prolog Compactor Chuck Kring - MakeArray Bob Mayo - MochaChip Sep 10 INTERACTIVE EDITORS David Harrison - VEM: An Interactive Graphics Environment for OCT Ping-San Tzeng - EDISTIX: A Virtual-Grid Symbolic Layout Editor Gaetano Borriello - WAVES: A Waveform Editor for Describing Circuit Interfaces Sep 17 PARALLEL COMPUTATION George Jacob - Multiprocessor Direct-Method Circuit Simulation Don Webber - Multiprocessor Relaxation-Based Circuit Simulation Andrea Casotto - Parallel Simulated Anneling on a Shared Memory Multi-Processor Srinivas Devadas- Topological Optimization via Simulated Annealing on the Sequent Multi-Processor Sep 24 AUTOMATIC LOGIC SYNTHESIS Richard Rudell - Synthesis Overview & Multiple-level Minimization Russ Segal - BDSYN and BDNET: Input Languages for Synthesis Albert Wang - Decomposition and Factoring in MIS Greg Whitcomb - Logic Synthesis Using Simulated Annealing Oct 01 CAD DATA BASES Peter Moore - OCT: A Data Manager for VLSI Ellis Chang - The Version Server: A Decoupled Data Manager For CAD David Gedye - The Design of a Browser for the Version Server Oct 08 ROUTING Karti Mayaram - CHAMELEON: A Multi-layer Channel Router Hyunchul Shin - MIGHTY: A Detailed Router Using Rip-up and Reroute Oct 15 THE MOSAICO LAYOUT SYSTEM Fabio Romeo - Overview of Mosaico: An Integrated System for Placement and Routing of Macro-Cells Andrea Casotto - Placement and Floorplanning Mitch Igusa - Routing Channel Definition Faye Marron - Channel Router and Channel Server Oct 22 THE MOSAICO LAYOUT SYSTEM (Part II) Hormoz Yagutiel - Power and Ground Router Gopal Srinath - Global Router Jeff Burns - SPARCS: A Constraint-Based Symbolic Layout Spacer Hyunchul Shin - Two-dimensional Compaction by Zone Refinement Nov 05 PLACEMENT & ROUTING - GLOBAL APPROACHES Jon Frankle - Circuit Placements by Eigenvector Decomposition Antony Ng - RanTer: A Linear Program Global Router Nov 19 FACULTY PANEL ON FUTURE DIRECTIONS Faculty Panel - Alberto Sangiovanni-Vincentelli, Carlo Sequin, Randy Katz, Richard Newton Nov 26 LAGER: AUTOMATIC LAYOUT GENERATION OF DSP ICs FROM HIGH-LEVEL DESCRIPTIONS Rajeev Jain - Overview of design methodologies for DSP ICs in Lager Chuen-Shen Shungi - Structural interface for Lager Syed Khalid Azim - Customizable control unit for Lager generated DSP architectures. Mani Bhushan Srivastava - Automatic module layout generation for DSP ICs in Lager Dec 03 IC LAYOUT RESEARCH IN PROF. KUH'S GROUP Wei-Ming Dai - Simultaneous Floor Planning and Global Routing Howard Chen - Gridless, Variable Width Channel Router Xiao-Ming Xiong - Efficient, Intelligent Channel Spacer Jan 28 CONNECTION MACHINE APPLICATIONS Don Webber - Circuit Simulation Andrea Casotto - Parallel Simulated Annealing for the Placement of Standard-Cells Feb 11 NEW MAGIC INTERACTIVE ROUTER Michael Arnold - The New Magic IROUTER: An Interactive Maze Router With Hints Feb 11 LOGIC VERIFICATION Srinivas Devadas - Verification of Sequential Machines at Differing Levels of Abstraction Tony Ma - Combinational Logic Verification Algorithms and Their Parallel Implementation Feb 18 TESTING (DIGITAL & ANALOG) Tim Cheng - Partial Scan Design for Sequential Circuit Testing Linda Milor - Efficient Go/No-go Testing of Analog Circuits Feb 25 MOCHA CHIP Robert Mayo - Mocha Chip: A Graphical Programming System for IC Module Assembly Mar 04 HIGH-LEVEL SYNTHESIS (Part I) William Bush - High Level Synthesis in ASP Gaetano Borriello - JANUS: An Interface Transducer Synthesizer Mar 18 HIGH-LEVEL SYNTHESIS (Part II) Suresh Krishna & Timothy Hu - Automated Phase Assignment and Scheduling for VLSI Datapath Pipelines Apr 15 CONSTRAINT-BASED PLACEMENT TOOLS Michael Jackson - Timing-Driven Routing for Building Block Layout Chuck Kring - Mkarray - An Array Assembler Apr 22 CIRCUIT OPTIMIZATION Jyuo-Min Shyu - Optimization-Based Transistor Sizing Fred Obermeier - Electrical and Physical Layout Improvement Apr 29 ABSTRACT TIMING VERIFICATION David Wallace - Abstract Timing Verification for Synchronous Digital Systems May 06 KNOWLEDGE-BASED TOOLS Theo Kelessoglou- A Knowledge-Based SPICE Environment Rick Spickelmier- A Knowledge-Based Circuit Critic "EE298-7 --- VLSI CAD Seminar --- 1987-8" Mar 16 1988 The Professors' State of the Art Address "High-Level Synthesis: CAD for the 90s" Robert Brayton, Richard Newton, Carlo Sequin Apr 6 1988 "Logic Synthesis: A Mature Technology" Robert Feretich, Integrated CMOS Systems May 4 1988 The BOLD Multilevel Synthesis Project Recent Advances and the Prognosis for Industrial Strength Controllers G. D. Hachtel, Department of ECE, University of Colorado, Boulder, CO "EE298-7 --- VLSI CAD Seminar --- 1988-9" Oct 18 1988 Provably Correct Critical Paths Patrick C. McGeer, EECS Department/CS Division, UC-Berkeley Feb 1 1989 Symbolic Dynamics and Finite State Machines Roy Adler, Math. Sciences Dept., IBM Watson Research Center Feb 17 1989 Improving the Iteration Bound of Finite State Machines HorngDar Lin, UC/Berkeley Feb 22 1989 The H-code Project Tom Laidig, UC Berkeley Mar 1 1989 A MODIFIED APPROACH TO TWO-LEVEL LOGIC MINIMIZATION Abdul A. Malik, UC Berkeley EECS Mar 8 1989 The BLIS Behavior-to-Logic Interactive Synthesis System Gregory S. Whitcomb, EECS Department, UC-Berkeley Mar 31 1989 Mesochronous Interconnection in Digital Systems D.G. Messerschmitt, UC Berkeley, EECS Apr 19 1989 ISSUES ON AUTOMATION OF VLSI DESIGN MANAGEMENT AND PROPOSAL FOR A SOLUTION Andrea Casotto, EECS Department, UC-Berkeley May 3 1989 Factoring Logic Functions Albert R. Wang, CS Division, UC-Berkeley May 8 1989 The CAD Manifesto Carlo Sequin, Computer Science Division, U.C. Berkeley May 30 1989 Behavioral Synthesis at IMEC Synthesis of Asynchronous Interface Circuits Peter Vanbekbergen, IMEC Lab., Leuven, Belgium "EE298-7 --- VLSI CAD Seminar --- 1989-90" Sep 27 1989 Performance-Driven Layout of Cell-Based IC's Mike Jackson, U. C. Berkeley Oct 4 1989 Efficient Manipulation of Boolean Functions Richard Rudell, Synopsys, Inc. Nov 29 1989 CROSSCHECK: A CELL BASED VLSI TESTABILITY SOLUTION Tushar Gheewala, CrossCheck Technology, Inc. Dec 6 1989 Relative Scheduling under Timing Constraints in High-level Synthesis Giovanni De Micheli, Computer Systems Laboratory, Stanford University Feb 7 1990 FORMAL DEVELOPMENT and VERIFICATION of VLSI Bob Kurshan, AT&T Bell Labs., Murray Hill Mar 5 1990 ROAD: a ROuter for Analog Design Enrico Malavasi, University of Bologna - Italy Mar 7 1990 Real-time behavior of asynchronous systems David Dill, Stanford University Mar 16 1990 "Effective Use of Transformations in High Level synthesis" Miodrag Potkonjak, UC Berkeley Mar 21 1990 EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Product Expressions for Multiple-Valued Input Two-Valued Output Functions Tsutomu Sasao, Dept. of CS and EE, Kyushu Institute of Technology, Japan Mar 28 1990 A Timing Verification Algorithm for Level-Clocked Circuitry Alexander T. Ishii, Laboratory for Computer Science, MIT Apr 4 1990 MARS (Multi-layer Area Routing System) Mitch Igusa, U. C. Berkeley Apr 11 1990 SLIP: System-Level Interactive Partitioning Chuck Kring, U. C. Berkeley "EE298-7 --- VLSI CAD Seminar --- 1990-91" Sep 19 1990 Levels of Abstraction in HDL Synthesis: Practical and Fanatical Emil Girczyc, Synopsys Inc. Sep 26 1990 SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM SIGNAL TRANSITION GRAPHS Tam-Anh Chu, Cirrus Logic Oct 3 1990 SYNTHESIS OF VERIFIABLY HAZARD-FREE ASYNCHRONOUS INTERFACE CIRCUITS L. Lavagno, Dept. of EECS, U. C. Berkeley Oct 17 1990 Segmented Channel Routing Architectures for FPGAs Jonathan Greene, Actel Oct 24 1990 The Third Generation of Field Programmable Gate Arrays Stephen Trimberger, Manager of Advanced Development, Xilinx, Inc. Nov 16 1990 High-Level Specification for Control-Oriented Systems Michael C. McFarland, SJ, AT&T Bell Labs and Boston College Dec 5 1990 Combinational Logic Optimization Techniques in Sequential Logic Synthesis Sharad Malik, C. S. Division, U. C. Berkeley Jan 30 1991 Bruce Bourbon, President/CEO, Vertex Semiconductor Corporation Jan 30 1991 Hardware Emulation: A New Technique for Functionally Validating Designs Thomas S. Payne, Quickturn Systems, Inc. Feb 6 1991 Modeling and Verifying Real-time Systems Rajeev Alur, Stanford University Mar 6 1991 Embedded Real-Time Control systems Design Macs Chiodo Apr 3 1991 PARALLELISM EXTRACTION AND PROGRAM RESTRUCTURING FOR PARALLEL SIMULATION OF DIGITAL SYSTEMS Beverly Vellandi, University of Colorado at Boulder Apr 10 1991 The Role of Theorem Provers in Hardware Verification Paul Loewenstein, Manager Formal Verification, Mitsubishi Electronics America Apr 17 1991 Algorithms in new IBM logic synthesis system Lukas van Ginneken, IBM Thomas J. Watson Research Center Apr 24 1991 Bill Lin (Representing and Manipulating Equivalence Classes Efficiently) Mark Beardslee (Logic Partitioning and Decomposition Based on Inter-partition Communication) May 1 1991 Verification of the MIPS R4000 Microprocessor A Novel Approach: Booting the operating system on a behavioral model of the microprocessor Amir Nayyerhabibi, Andrew Peebles, Mike Dove May 22 1991 PERFORMANCE AND TESTABILITY INTERACTIONS IN LOGIC SYNTHESIS Alexander Saldanha, U.C. Berkeley Jul 25 1991 ASYNCHRONOUS FINITE STATE MACHINE SPECIFICATION Tam-Anh Chu, Cirrus Logic R&D "EE298-7 --- VLSI CAD Seminar --- 1991-92" Sep 4 1991 Object-Oriented Database Management Systems and their use in CAD Rick Spickelmier, Objectivity Sep 18 1991 ITEM (If-then-else Minimizer) UCSC's Multi-level Logic Minimizer Kevin Karplus, University of California Santa Cruz Sep 15 1991 Massively Parallel Computing for CAD Alberto Sangiovanni-Vincentelli Oct 2 1991 RITUAL: An Algorithm for Performance-Driven Placement of Cell-based ICs Arvind Srinivasan, UC Berkeley Oct 4 1991 Neural Organization of the Locomotive Oscillator W.L. Miranker, IBM T.J. Watson Research Lab Oct 9 1991 Applications of Term Rewriting to Circuit Verification Kathy Yelick, UC Berkeley, Computer Science Division Oct 16 1991 Optimal Module Generation for Semi-custom Design Masahiro Fukui, UC Berkeley (Visiting Industrial Fellow Matsushita Elec. Ind.) Oct 23 1991 Area, Performance, and Testability Tradeoffs in Logic Synthesis Alexander Saldanha, U.C. Berkeley Oct 30 1991 Floating-Delay Test Generation Albert Wang, Synopsys Nov 1 1991 Asynchronous Synthesis Ken Stevens, University of Calgary Nov 6 1991 Technology dependent optimization, or What is a gate? Ewald Detjens, President and CEO, Exemplar Logic Nov 8 1991 High-Level Synthesis from VHDL with Tight Timing Constraints Michael Payer, Siemens AG, Corporate Research and Development, Munich, Germany Nov 18 1991 Timing Issues in Digital System Design Karem A. Sakallah, University of Michigan Nov 19 1991 The CIRCAL System: A Process Algebra for Hardware Verification George McCaskill, University of Strathclyde, Scotland Nov 19 1991 ANALOG CIRCUIT LAYOUT COMPACTION: PRESENTATION OF ISSUES AND GENERAL DISCUSSION OF THE BERKELEY CONSTRAINT-DRIVEN APPROACH Eric Felt Nov 20 1991 Specification and Verification of Platoon Maneuvers Protocols for IVHS Sonia Sachs, UC Berkeley Nov 22 1991 Technology Mapping and Layout Synthesis of DCVS Carly Wong Nov 25 1991 High-Level Synthesis : An Overview Sabine Maerz, Siemens Corporate Research & Development, Munich, Germany Nov 26 1991 Design Automation in the Soviet Union: History and Status Dr. Alexander Stempkovsky, USSR Academy of Sciences, Research Institute of CAD for VLSI Dec 4 1991 Has CAD for VLSI Reached a Dead End? A. Richard Newton, Department of EECS, U.C. Berkeley Jan 23 1992 PROBABILISTIC DESIGN VERIFICATION Donald S. Fussell, Department of Computer Sciences, UT Austin Jan 27 1992 HARDWARE EMULATION: A NEW TECHNIQUE FOR VERIFYING DESIGN FUNCTIONALITY Thomas Payne, Quickturn Systems Feb 3 1992 MODEL-BASED FAULT DIAGNOSIS OF DIGITAL CIRCUITS Peter Cheung, Imperial College of Science and Technology, University of London Feb 5 1992 Overview of Asynchronous Synthesis Research Luciano Lavagno, Cho Moon, UC Berkeley Feb 12 1992 A New Exact and Heuristic Minimizer for Logic Functions Patrick C. McGeer, UC Berkeley Feb 19 1992 Optimal Retiming of Level-Clocked Circuits Carl Ebeling, University of Washington Feb 19 1992 RELATIONAL DESCRIPTIONS OF DIGITAL CIRCUITS Eduard Cerny, Dept. d'informatique et de recherche operationnelle, Universite de Montreal Feb 26 1992 Synthesis and Optimization of Synchronous Logic Circuits from Recurrence Equations Giovanni DeMicheli, Stanford University Mar 4 1992 CAD for Micro Electromechanical Systems Kris Pister, Robotics/BSAC, UC Berkeley Mar 18 1992 High Performance Simulation of Hardware Description Languages Gary York, Cadence Design Systems Apr 1 1992 The Role of Programmable Interconnect in System-level Verification and Integration Chuck Kring, Aptix Corporation Apr 1 1992 ASIC Design System: A Logic Synthesis Product Barry Shackleford, Hewlett Packard Laboratory Apr 3 1992 Integrated Placement and Routing for VLSI Layout Synthesis and Optimization Ping-San Tzeng Apr 6 1992 CHIPAIDE - An Analog CAD Environment Peter Cheung, Imperial College, University of London Apr 8 1992 TEST GENERATION FOR SEQUENTIAL CIRCUITS Abhijit Ghosh, Mitsubishi Electronics America Ltd. Apr 13 1992 ON CIRCUIT PARTITIONING AND THE INTRINSIC RENT PARAMETER Andrew B. Kahng, Dept. of Computer Science, UC Los Angeles Apr 13 1992 Approaches to the State Explosion Problem Ken McMillan, Carnegie Mellon University Apr 20 1992 LAYOUT COMPACTION ALGORITHM AIMING AT IMPROVED CIRCUIT PERFORMANCE Akira Onozawa, NTT LSI Laboratories Apr 22 1992 Tools versus Silicon: An FPGA Architecture Designed to Fit CAE Tools Laurence H. Cooke, Crosspoint Solutions Apr 23 1992 Current Trends in Software Testing Technology Mindcraft Inc, Claudia De Blauw Apr 27 1992 A BOARD-LEVEL FIELD PROGRAMMABLE INTERCONNECT SOLUTION H-F. Stephen Law, Aptix Corporation Apr 29 1992 Data-flow/Event Graphs Gregory Whitcomb, UC Berkeley May 6 1992 The High-Level Synthesis of Microprocessors Using Instruction Frequency Statistics William R. Bush May 13 1992 THE EFFECTIVENESS OF DIFFERENT TYPES OF TEST SETS ON QUALITY LEVELS: HOW MANY FAULT COVERAGES DO WE NEED? Peter C. Maxwell, Design Technology Center, Integrated Circuits Business Division, Hewlett-Packard Company May 14 1992 Synthesis of Multi-Level Logic Circuits for Complete Robust Path Delay Fault Testability Niraj K. Jha, Princeton University "EE298-7 --- VLSI CAD Seminar --- 1992-93" Sep 2 1992 A New Approach to Prototyping Distributed, Time Sensitive Systems David C. Luckham, Stanford University Sep 9 1992 GRAPH ALGORITHMS FOR EFFICIENT CLOCK SCHEDULE COMPUTATION Narendra Shenoy, UC Berkeley Sep 16 1992 Performance Optimization of Digital Circuits Kanwar Jit Singh, Dept. of EECS, Univ. of California, Berkeley Sep 23 1992 CAD for Molecular Discovery Steven Teig, BioCAD Corporation Sep 30 1992 Formal Verification Using Language Containment Ramin Hojati, Dept. of EECS, Univ. of California, Berkeley Oct 7 1992 Formal Verification Using Computation Tree Logic Tom Shiple, Dept. of EECS, University of California, Berkeley Oct 14 1992 Analysis and Verification of VAL/VHDL Using Waveform Algebra Larry Augustin Oct 21 1992 FORMAL VERIFICATION OF REAL-TIME SYSTEMS Felice Balarin, UC Berkeley Oct 22 1992 Design, Realization and Characterization of MCM-D for High Speed Digital Circuits Eric Beyne, IMEC, Belgium Oct 28 1992 An Application of the Reactive Computing Model to the VHDL Language Wendell Baker, U. C. Berkeley Nov 2 1992 Symbolic Verification of Sequential Circuits Synthesized with CALLAS Michael Payer, Siemens Corporate Research and Development Nov 4 1992 Logic Synthesis for Programmable Gate Arrays Rajeev Murgai, UC Berkeley Nov 12 1992 Integration of Signal Processing Systems on Heterogeneous IC Architectures Gert Goossens, IMEC, Belgium Nov 12 1992 System-level Design Support for Mixed Control-Intensive and Signal Processing Systems Bill Lin, IMEC, Belgium Nov 13 1992 Partitioning and Functional Analysis of Digital Static CMOS Circuits Uwe Huebner, German National Research Center for Computer Science Institute for System Design Technology Nov 18 1992 Processor Validation at Intel Tom Shott, Computer Architect, INTeL Corporation Nov 24 1992 Testing: Relationships to logic synthesis and optimization Alexander Saldanha Dec 2 1992 Delay-fault coverage, test set size, and performance tradeoffs Alexander Saldanha Dec 9 1992 Synthesis of Asynchronous Circuits from Signal Transition Graphs Luciano Lavagno, UC Berkeley Jan 15 1993 A Parallel Lookahead Line Search Router with Automatic Ripup-and-reroute Hiroshi Date, date@icot.or.jp A Standard Cell Placement Program Based on the Time-homogeneous Parallel Simulated Annealing Hiroshi Date, date@icot.or.jp Parallel Logic Simulator using the Time Warp Mechanism Yukinori Matsumoto, yumatumo@icot.or.jp Jan 27 1993 Approximating Continuous Time Jerry R. Burch, Computer Science Department, Stanford University Feb 3 1993 Physically Realizable Gate Models Paul R. Stephan, UC Berkeley Feb 10 1993 SPECTRAL ALGORITHMS: A New Approach to Some Discrete Optimization Problems in Scientific Computing Horst D. Simon, NASA Ames Research Center Feb 17 1993 Analog CAD at Berkeley: New Methodologies for Top-down Automated Design Eric Felt, Dept. of EECS, U.C. Berkeley Feb 24 1993 Context-Based ASIC Data-Path Synthesis Steve Kelem, Xilinx, Inc. Mar 3 1993 Automatic Test Pattern Generation for Sequential Circuits Carol Wawrukiewicz, Dept. of EECS, UC Berkeley Mar 17 1993 Digital Design Derivation: Foundations and Experiments Steven D. Johnson, Computer Science Department, Indiana University Mar 26 1993 HYBRID AUTOMATA Tom Henzinger, Cornell Univ. Mar 31 1993 System Synthesis using Reprogrammable Components Rajesh K. Gupta, Stanford University Apr 7 1993 A New Library-based, Performance-oriented Mapper for LUT FPGAs Narasimha B. Bhat, Dept. of EECS, U. C. Berkeley Apr 12 1993 On the Effective Design of High-Performance Routing Trees Andrew B. Kahng, Computer Science Dept., UC Los Angeles Apr 14 1993 Technology Decomposition and Mapping for Low Power Massoud Pedram, University of Southern California Apr 21 1993 Logic Optimization, Machine Learning and Occam's Razor Arlindo Oliveira, Dept. of EECS, UC Berkeley Apr 26 1993 CAD for Multi-Chip Modules Wayne Wei-Ming Dai, Computer Engineering, UC Santa Cruz Apr 28 1993 A Design Methodology for Hardware/Software Codesign of DSP Applications Asawaree Kalavade, Dept. of EECS, UC Berkeley May 5 1993 Communication-Based Logic Partitioning Mark Beardslee, Dept. of EECS, UC Berkeley May 5 1993 New Directions in Practical Large-Scale Optimization Andrew B. Kahng, Computer Science Dept., UC Los Angeles May 12 1993 Unifying Synchronous/Asynchronous State Machine Synthesis Kenneth Y. Yun, Computer Systems Laboratory, Stanford University May 28 1993 Designing an Analog Computational Sensor with Continuous-Valued Lukasiewicz Logic Arrays Jonathan Mills, Computer Science Department, Indiana University Jun 11 1993 Application of 0-sup-BDDs for Logic Synthesis Shin-ichi Minato, NTT LSI Laboratory, Japan "EE298-7 --- VLSI CAD Seminar --- 1993-94" Sep 8 1993 Optimization of Interacting Finite State Machines Yosinori Watanabe, Department of EECS, University of California at Berkeley Sep 15 1993 Input Don't Care Sequences in FSM Networks Huey-Yih Wang, Department of EECS, University of California at Berkeley Sep 22 1993 Two Problems in Synthesis for Table Look Up Architectures Rajeev Murgai, Department of EECS, University of California at Berkeley Sep 29 1993 An Exact Optimization of Acyclic Two-Level Sequential Circuits Ellen M. Sentovich, Department of EECS, University of California at Berkeley Oct 1 1993 Automatic Test Program Generation for Pipeline Controllers Tsuneo NAKATA, Fujitsu Laboratories Ltd. Oct 6 1993 Synthesis of Multilevel Combinational Circuits from Binary Decision Diagrams Nagisa Ishiura, Dept. EECS, UC Berkeley, Visiting scholar from Dept. Information Systems Engineering, Osaka University Oct 11 1993 A Combined Approach to the Generation of Test for Delay and Stuck-At Faults Franco Fummi, Politecnico di Milano Oct 13 1993 Exact Sequential Timing Analysis for FSM's Using Timed Boolean Functions William K. Lam, University of California at Berkeley Oct 20 1993 A Summary of Research Projects on CAD for VLSI's Alexander Saldanha, University of California at Berkeley Oct 27 1993 A Fully Implicit Algorithm for Exact State Minimization Timothy Kam and Tiziano Villa, University of California at Berkeley Oct 29 1993 A functional representation method for delay characteristics of combinational circuits Atsushi Takahara, Visiting Industrial Fellow from, Nippon Telegraph and Telephone Corporation, LSI Laboratories, Atsugi-Shi, Japan Nov 3 1993 Monte Carlo Device Simulation for Massively Parallel Computers Henry Sheng, University of California, Berkeley Nov 12 1993 Boolean Manipulation with Free BDD's. First Experimental Results. Christoph Meinel, FB IV -- Informatik, Universit"at Trier, Germany Nov 12 1993 Scheduling of Control Wayne Wolf, Dept. of Electrical Engineering, Princeton University Nov 12 1993 Performance Driven Physical Design Automation: Requirements and Challenges Dr. Xiao-Ming Xiong, Cadence Design Systems Nov 12 1993 An Optimal Cardinality-Constrained Territory Map and Its Application to a Clock Net Reassignment Problem Prof. Shuji Tsukiyama, Chuo University, Japan Nov 15 1993 THE NELSIS CAD FRAMEWORK: A LIGHT-WEIGHT SYSTEM FOR TOOL INTEGRATION AND DESIGNER ASSISTANCE Pieter van der Wolf, Delft Institute of Microelectronics and Submicron technology (DIMES), Delft University of Technology, The Netherlands Nov 17 1993 Applications of Massively Parallel Processors to TCAD Problems Eric Tomacruz, U.C. Berkeley Dec 1 1993 Hardware/Software Codesign for Real Time Embedded Controllers Paolo Giusto, Magneti Marelli, Italy, Visiting Industrial Fellow at U.C. Berkeley Dec 1 1993 Works in Self-Timed Design in Russia Prof. Victor Varshavsky, University of AIZU, Japan, formerly STRASSA, St. Petersburg, Russia Jan 31 1994 ANALYTIC CIRCUIT SIMULATION FOR LARGE-SCALE, SUB-MICRON ICS Andrew T. Yang, Dept. of Electrical Engineering, University of Washington Feb 2 1994 HSIS: A Formal Verification Tool Based on BDD's Ramin Hojati, University of California at Berkeley Feb 9 1994 Comparative Approach to Processor Verification Using Symbolic Model Checking Nagisa Ishiura, Dept. Information Systems Engineering, Osaka University, Osaka Japan Feb 16 1994 Circuit Clustering for Delay Minimization Martin D. F. Wong, Department of Computer Sciences, University of Texas at Austin Feb 16 1994 A Versatile Data Path Synthesis Approach Based on Heuristic Search Prof. Anshul Kumar, Dept. of Computer Science and Engineering, Indian Institute of Technology, New Delhi, India. Feb 23 1994 Bug Identification of a Real Chip Design by Symbolic Model Checking Ben Chen, FUJITSU DIGITAL TECHNOLOGY LTD., 2-3-9, Shin-yokohama, Kouhoku-ku, Yokohama 222, Japan. Feb 25 1994 A NEW APPROACH TO FAST MOS TIMING SIMULATION WITH DIRECT EQUATION SOLVING OF A GENERAL CIRCUIT PRIMITIVE Prof. Sung-Mo (Steve) Kang, Department of Electrical and Computer Engineering and, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Mar 2 1994 Formalization of Asynchronous Technology Mappings Paul Stephan, UC Berkeley Mar 14 1994 Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation Prof. Qingjian Yu, Visiting Scholar from Nanjing Univ. of Science & Technology Mar 14 1994 Symbolic Model Checking for Linear-Time Temporal Logic Dr. Kiyoharu Hamaguchi, Carnegie Mellon University, On leave from Kyoto University Mar 16 1994 Sequential Replaceability for Synchronous Designs Vigyan Singhal, UC Berkeley Mar 21 1994 High Speed and Low Power Clock Distribution Based on Area Pad Interconnection for Multi-Chip Modules Prof. Wayne Wei-Ming Dai, Computer Engineering, University of California at Santa Cruz Mar 23 1994 Simulation and Test Pattern Generation for Bridge Faults in CMOS ICs Tracy Larrabee, UC Santa Cruz Apr 6 1994 Automatic Verification of Pipelined Microprocessor Control Jerry R. Burch, Stanford University Apr 13 1994 Constrained System Partitioning Minshine Shih, UC Berkeley Apr 20 1994 Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool for Combinational CMOS Circuits Rick McGeer, Cadence Berkeley Laboratories Apr 27 1994 Techniques for Crosstalk Avoidance in the Physical Design of High-Performance Digital Systems Desmond Kirkpatrick, UC Berkeley May 4 1994 Dynamic Scheduling and Synchronization Synthesis of Concurrent Systems Under System-level Constraints Claudionor Coelho, Stanford University May 11 1994 FSM Synthesis for VLSI: Unified approach for State Assignment, Stack FSM Synthesis Chaker Sarwary, Paris University Jun 17 1994 Professor Fabio Somenzi from the University of Colorado at Boulder will be giving an overview of their latest research work in CAD, with emphasis on the low power work. Jun 24 1994 Partitioning Large Circuits Using Analytical Placement Techniques Bernhard M. Riess, Institute of Electronic Design Automation, Technical University of Munich "EE298-7 --- VLSI CAD Seminar --- 1994-95" Aug 31 1994 An Automatic Abstraction method for Hierarchical Designs Atsushi Takahara, Visiting Industrial Fellow from, Nippon Telegraph and Telephone Corporation, LSI Laboratories, Atsugi-Shi, Japan Sep 16 1994 Reuse of Design Procedure for Analog Circuit and Layout Design Hidetoshi Onodera, Associate Professor, Department of Electronics, Kyoto University, Japan Sep 21 1994 Finding the Maximum Power Cycle in Sequential Circuits Fabio Somenzi, University of Colorado Sep 28 1994 SOME DEVELOPMENTS IN HIGH-LEVEL MODELING AND SIMULATION OF MIXED-SIGNAL CIRCUITS Giorgio Casinovi, School of Electrical & Computer Engineering, Georgia Institute of Technology Sep 28 1994 Efficient and Robust Test Generation-Based Timing Analysis Karem A. Sakallah, Dept. of EECS, University of Michigan Oct 5 1994 Topics in synthesis and verification research - an industrial perspective Ewald Detjens, Exemplar Corporation Oct 12 1994 Nonlinear Control Synthesis: Basic Concepts Professor Marika De Benedetto, Department of Information and Systems, Universita' di Roma Oct 17 1994 Nonlinear Control Synthesis: Model Matching for Finite State Machines Professor Marika De Benedetto, Department of Information and Systems, Universita' di Roma Oct 19 1994 Advanced Verification Techniques Based On Learning Dr. Jawahar Jain, Fujitsu Laboratories of America, Inc. Oct 31 1994 Interconnect Analysis for Electronic Packaging Zheng-Fan Li, Shanghai Chiao-Tong Unversity Nov 2 1994 Performance Analysis of Embedded Software Using Implicit Path Enumeration Sharad Malik, Department of Electrical Engineering, Princeton University Nov 10 1994 On Modeling Top-Down VLSI Design Joachim Altmeyer and Bernd Schuermann, Department of Computer Science, University of Kaiserslautern Nov 16 1994 Easily Searched Encodings for Number Partitioning Tom Ngo, Interval Research Corporation Nov 30 1994 A New Precorrected-FFT Algorithm for Accelerating the Iterative Solution of Potential Integral Equations Joel R. Phillips, Massachusetts Institute of Technology Dec 7 1994 Non-Sequential Tool Interaction Strategies for Sea-of-Gates Layout Synthesis Glenn D. Adams, U. C. Berkeley Jan 18 1995 An Introduction to Tcl/Tk Stephen Edwards, Berkeley CAD Group Jan 25 1995 Utilizing Symmetry when Model Checking under Fairness Assumptions: An Automata-theoretic Approach E. Allen Emerson, University of Texas at Austin Feb 1 1995 Hierarchical Models of Synchronous Circuits David L. Dill, Stanford University Feb 8 1995 Logic Verification and Synthesis with Temporal Logic Masahiro Fujita, Fujitsu America Laboratories Feb 15 1995 A Design Environment for Multi-Million Transistor Chip Design: Created by Designers for Designers Mehdi Hatamian, Silicon Design Experts, Inc. Feb 22 1995 New Results in BDD-Based Scheduling Forrest Brewer, UC Santa Barbara Mar 1 1995 Computing with Continuous Change Vijay Saraswat, Xerox PARC Mar 7 1995 Software Synthesis for Hardware/Software Co-design of Embedded Systems Alberto Sangiovanni-Vincentelli, UC Berkeley Mar 15 1995 System-Level Design Automation: The Unified System Construction Project Alice C. Parker, Vice Provost for Research, University of Southern California Mar 22 1995 Computer-Aided Verification of Infinite-State Systems Thomas A. Henzinger, Cornell Univ. Apr 5 1995 A Case for NOW Dave Patterson, UC Berkeley Apr 12 1995 Higher Level Design Tools Raul Camposano, Synopsys Apr 19 1995 How Matrix-Free Iterative Methods Have Changed Computer Simulation of Circuits, Devices, Interconnect, and Micro-Electro-Mechanical Systems Jacob White, MIT Apr 26 1995 Dataflow Process Networks Tom Parks, UC Berkeley May 3 1995 Some problems in submicron technology and their effect on design methods and CAD tools Antun Domic, Cadence Design Systems May 5 1995 Research Developments in Analog CAD at KU-Leuven Georges Gielen, KU-Leuven May 10 1995 Code Generation and Optimization for Embedded DSP Processors Stan Y. Liao, MIT May 12 1995 Finite State Machines and Differential Equations: using dynamical systems theory to understand VLSI circuits Mark Greenstreet, University of British Columbia Jun 2 1995 Word Level Model Checking Edmund M. Clarke, Carnegie Mellon University Jun 16 1995 Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits K. Lampaert, KU Leuven Jun 23 1995 A Method of Delay Estimation and Optimization for Technology-Independent Logic Circuits Yuichi Nakamura, NEC, Japan