This is release 1.1 of MVSIS, a system for multi-value logic network 
optimizations. The current release includes a binary executable
for Redhat Linux 6.1 (or Linux kernel 2.2.x and glibc 2.1) and higher,
Solaris and Windows.

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What's new in MVSIS 1.1:

1. Node minimization using complete flexibility (complete_simplify)
   
2. Node minimization and collapsing using ISOP representations (isop)

3. Encoding Binary Decoding (EBD) mapping for decomposition and fast 
   extract, which encodes the MV algebraic problems into binary ones and
   applies fast binary algorithms ported from SIS.

4. Bi-decomposition of MV logic networks into MIN/MAX/LIT devices.

5. Code generation for fast simulation and embedded software implementation.
   The BLIF-MV format is extended to support data-path. Tools are provided
   to generate such BLIF-MV files from Esterel programs.

6. Use of priority don't cares for software synthesis and POST algebra.

7. Equivalence checking by containment of relations (verify)

8. Bug fixes.

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To set up MVSIS:

1. Download the binary distribution from URL and store in /tmp (for example)
   http://www-cad.eecs.berkeley.edu/mvsis

2. Move to where you would like to put MVSIS  and unpack the distributions:

	% cd /home/mvsis                                  # for example
	% gzip -dc /tmp/mvsis-linux.tgz | tar xf -

3. MVSIS expects to find master.mvsisrc, a .nawk file, and a directory of 
   help files in the directory given by the global variable "lib_path".
   These are configured in a script file ".mvsisrc", which will be sourced
   each time MVSIS is invoked. It will be automatically generated by an 
   installation script "install" and stored in the user's default home 
   directory. 

        % cd mvsis-linux/
        % ./install	(make sure your type "./install" and not "install")


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# Files in this distribution

README		This file.
mvsis		Binary executable for Linux
install		Installation script to set up the correct library path.

share/master.mvsisrc
		A MVSIS script designed to be run automatically at start-up:
		contains aliases for commonly used commands and some default
		parameter settings.
share/mvsis.script	
share/mvsis.scriptb
share/mvsis.scriptd
		Example optimization scripts which can be executed by
                command "source".
share/help/*	
		ASCII documentation for each MVSIS command, accessible through
		the "help" command in MVSIS. This is available only when the 
		global variable lib_path is setup properly by command "set".

examples/	
examples/mv/*	
		Multi-valued logic networks coming from the VIS distribution,
		machine learning examples from Portland, and hand crafted ones.
examples/binary/*
		Binary logic networks coming from the SIS distribution.
examples/seq/*
		Sequential logic networks.
examples/efsm/*
		EFSM examples with data-path elements.

doc/
doc/mvsis_manual.ps	
doc/mvsis_manual.pdf	
		MVSIS users manual and the description of all optimization commands.
doc/genc_manual.ps
		Code generation manual and the description of the design flow.
doc/blifmv.ps	
		Description of the BLIF-MV file format


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List of MVSIS commands:

0. New commands
   isop collapse_global complete_simplify 
   ebd_decomp ebd_fx sis_eliminate
   encode2 verify write_blif
   compress gen_c bidecomp

1. IO operations and miscellaneous commands:
   read_blif read_blifmv write_blifmv delete 
   help source alias unalias set unset echo 
   runtime usage undo save history quit
   chng_name reset_name

2. print out networks:
   print print_altname print_level
   print_stats print_io print_range 
   print_factor print_value print_part_value
   _print_version

3. algebraic methods:
   decomp factor fx resub

4. don't care methods:
   simplify fullsimp

5. network optimizations:
   sweep eliminate collapse elim_part
   merge pair_decode encode reset_default

6. verification
   gen_vec simulate validate
   qcheck

7. sequential network support
   extract_seq_dc


Known bugs:
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1. ebd_decomp (ebd_fx) produces fatal error if called after command
   bidecomp, due to name conflicts. A bug fixed version will be released
   in the near future.

2. In the input BLIF-MV files, a latch cannot have the same name as any
   primary inputs or outputs. 


Contact:
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the MVSIS group (mvsis-devel@ic.eecs.berkeley.edu)
May. 2002