| |
|
|
A Constraint-Driven Placement Methodology for Analog Integrated Circuits
Abstract:A new constraint-driven methodology for the placement of analog IC's is described. Electrical performance specifications are automatically translated into constraints on the layout parasitics. These constraints and the sensitivity information of the circuit are then used to control a Simulated Annealing-based placement algorithm. At each step of the annealing a fast check on performance degradations is performed to guarantee that the tool has the necessary robustness. |
| Contact |
| ©2002-2018 U.C. Regents |