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Imposing Tight Specifications on Analog IC's Through Simultaneous Placement
and Module Optimization
Abstract:
Techniques are presented for simultaneous placement and module
optimization for analog ICs. An algorithmic approach to module
generation provides alternative sets of modules, optimized with
respect to performance but with different trade-offs among area,
parasitics and matching.
A Simulated Annealing algorithm performs the placement, selecting
among the available configurations the one that best fulfills all
performance and geometric requirements.
Compared to standard approaches,
the flexibility of placement is considerably increased, thus allowing
the enforcement of tighter specifications.
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