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Simultaneous Placement and Module Optimization of Analog IC's
Abstract:
New placement techniques are presented which substantially improve the
process of automatic layout generation of analog IC's.
Extremely tight specifications can be enforced on high-performance
analog circuits by using simultaneous placement and module optimization.
An algorithmic approach to module generation provides alternative
sets of modules optimized with respect to area and performance but
equivalent in terms of parasitics and topology.
The final module selection is performed during the placement phase,
based on Simulated Annealing.
The flexibility of the annealing algorithm has been significantly
improved, thus making it possible to more efficiently exploit the
trade-offs between area, parasitics and matching.
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