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Generalized Constraint Generation for Analog Circuit Design
Abstract:
A general methodology is presented for the generation of a complete set of
constraints on interconnect parasitics, parasitic mismatch and on the
physical topology of analog circuits.
The parasitic and matching constraints are derived from high-level
performance specifications by means of sensitivity analysis in time
and frequency domain using quadratic optimization. Topological
constraints are obtained by using sensitivity and matching information
on devices and interconnect as well as graph-based techniques to
extract the necessary geometric information.
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