Performance-Driven Compaction for Analog Integrated Circuits


Abstract:

This paper describes a new approach to layout compaction of analog integrated circuits which respects all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. Our approach consists of two stages: a fast constraint-graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets.
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