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An Efficient Methodology for Symbolic Compaction of Analog IC's with Multiple Symmetry Constraint
Abstract:
An efficient approach to the symbolic compaction of analog
integrated circuits is presented. A fast graph-based algorithm
performs a preliminary compaction taking into account a set of basic
spacing constraints. The obtained configuration provides the starting
point for a linear program, which optimizes the layout introducing
multiple device and wire symmetry constraints. The efficiency and
robustness of this technique allows the use of our compactor for very
complex analog circuits with multiple symmetries and other performance
constraints.
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