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Symbolic Compaction with Analog Constraints
Abstract:
A tool named "sparcs" for compaction of integrated circuits with
analog constraints is presented. The approach is structured in two
steps. First, a robust and efficient constraint-graph compaction
algorithm produces a compacted layout quickly, where parasitics are
controlled so as to guarantee that the performance constraints are met.
Next, the layout produced by the first step is fed into a Linear
Programming solver which enforces symmetries and performs global
interconnect length minimization. The computational cost of the
iterative LP solver is modest because its initial state is the
configuration found by the constraint-graph algorithm, and only
symmetry constraints need to be enforced. With considerable
computational efficiency, this algorithm produces a
compacted layout which satisfies the high-level performance
constraints and is feasible for practical use within
industrial-strength analog synthesis systems. The use of such a
compactor allows one to relax the requirements on parasitic control
during placement and routing, thus improving the efficiency of the
entire layout design process.
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