The presentation schedule (and final reports) can be found here.
You will also have to submit a project report in the format of a conference paper, with a maximum limit of 6 pages, only readable size fonts! I will accept email submissions of .ps, .psgz, .ps.zip, .pdf formats only. Send the reports to me by 4pm on Tuesday the 11th. You will get 10% off if you are late. Zero points after 4pm on Wednesday the 12th. I will rely on my e-mail server time stamp! No exceptions, so consider submitting ahead of time!
You may design your favorite embedded system, work on theoretical results in the field of models of computation, define new design methodologies for specific sub-classes of systems, add point-tools to other design/analysis/synthesis/validation tools, etc.
Write a paragraph with your project proposal and a description of how you intend to proceed. You will need the authorization of the instructor.
You may even share the project for another class (if both instructors
agree), and with people not enrolled in class.
If you don't have a mentor, it is recommended that you work in pairs.
Contact Claudio Pinello (pinello@eecs.berkeley.edu)
see end of the list for individual projects
Metropolis information http://www.gigascale.org/metropolis/
This project studies variety of semantics of computation and communication often used in applications of embedded systems, and identifies how they can be modeled with the Metropolis meta- model. The meta-model is the internal mechanism used in the Metropolis design environment. It allows one to model different semantics uniformly using a common set of building blocks. This capability is essential in synthesis and verification, where heterogeneous components must be compared and their interaction needs to be analyzed.
The project considers the set of semantics supported in Ptolemy II, and writes a translator for each domain (corresponding to a particular semantics) so that a semantically equivalent meta-model representation can be generated.
Mentors: Yosinori Watanabe (watanabe@cadence.com)
Assigned to:
SPIN is a widely distributed tool for software verification developed at Bell labs. This project will make it possible to verify designs captured in Metropolis using SPIN.
Both Metropolis and SPIN use linear temporal logic to write properties to be verified. They both use single specification languages, but with different concerns. The challenge is to represent designs captured in Metropolis using SPIN's specification language, PROMELA. In this project, the semantics of the two languages will be carefully analyzed, and a Metropolis backend tool will be written in order to generate PROMELA from Metropolis. See the following site for information regarding to SPIN: http://netlib.bell-labs.com/netlib/spin/whatispin.html
Mentors: Yosinori Watanabe (watanabe@cadence.com)
Assigned to:
http://embedded.eecs.berkeley.edu/~zouh/ee249project.html
The Metropolis meta-model allows one to specify a design using multiple models of computation, and to refine both computation and communication down to the implementation level. It also allows one to specify constraints that limit cost, performance, power and so on, and that limit the set of legal functional refinements, using a mix of temporal and restricted propositional logics.
The goal of this project is to provide a graphical editor to navigate the structural hierarchy of a design developed using the meta-model, inspect the code and constraints associated with processes and communication channels, and generate the meta-model code to instantiate the objects in the hierarchy using the meta-model syntax (an extension of Java).
The task is to adapt an existing editor (a likely candidate is Vergil, from the Ptolemy II) to output a netlist using the meta-model syntax, including the specification of some refinements of computation and communication objects. Controlling the execution of a simulation could also be a nice addition in case more people volunteer.
Skills: java programming.
Mentors: Yosinori
Watanabe (watanabe@cadence.com)
Luciano Lavagno (luciano@ic.eecs.berkeley.edu)
Assigned to: Jiageng Ding and Hongjing Zou
The Metropolis meta-model allows one to specify a design using multiple models of computation, and to refine both computation and communication down to the implementation level. It also allows one to specify constraints that limit cost, performance, power and so on, and that limit the set of legal functional refinements, using a mix of temporal and restricted propositional logics.
An increasing number of safety-critical functionality are carried out by embedded processors. Examples include automotive steering and braking systems, nuclear plant control, airplanes control. These systems are required to deliver a satisfactory level of service despite a set of possible faults in the architecture. One key mechanism to achieve fault tolerance is the use of redundancy, i.e. multiple replicas of a given behavior can be executed at different times and/or on different resources. This redundancy must be managed and coordinated. Typically the level of redundancy depends on the possible architecture faults that we need to tolerate. So redundancy should be introduced only after a candidate architecture has been defined and should not be part of the initial behavioral description. This allows better reuse of the functionality and better design exploration. In order for this exploration to be viable, the introduction of redundancy should require little or no human intervention.
The goal of this project is to define a way to introduce redundancy in a semi-automatic way, using the refinement mechanisms provided in the meta-model. A Brake-by-Wire (electronic braking) system developed at BMW, will be used as a test case.
The task is to take standard redundancy patterns for behavior and communication and translate them in refinement patterns in Metropolis. Also the coordination of behaviors should be refined to include replica management. Schedule refinements seem appropriate to this end. If more people volunteer, scheduling optimizations may be devised for redundant netlist.
Skills: a bit of java programming or basic object oriented programming.
Mentors: Yosinori
Watanabe (watanabe@cadence.com)
Claudio Pinello (pinello@eecs.berkeley.edu)
Luigi Palopoli (luigip@eecs.berkeley.edu)
Assigned to: Dan Patterson
This project focuses on one of the most familiar problems in real-time control software design, i.e. how the performance of a controller is affected by architectural and mapping choices. Realistic and quantitative answers to this question during the early phases of the development are a precious tool for the product development. Tools like VCC/Polis permit very well to achieve an early assessment on certain types of performance metrics, such as the compliance with timing requirements, the power consumption, the utilization of computation and communication resources etc. On the other hand, control engineers commonly evaluate the performance of a behavioral design using other types of performance metrics regarding the quality of the closed loop dynamics (e.g. stability, robustness, rise-time, overshoot etc). Moreover, during the control synthesis, effects deriving from the architecture and from the mapping are not usually taken into account. As a consequence, in traditional approaches there is not any design phase when the system performance are evaluated taking into account both architectural and behavioral aspects. Such a multidisciplinary evaluation is made during the system prototyping (or even worse after its deployment in production units). However, in this phase, the cost of backward iteration to solve design problems can be very high. In order to alleviate these problems, the development of CAD tools offering the possibility of simulating continuous-time system and discrete-event controllers is of utmost importance. This project is aimed at studying the possibility of endowing the Metropolis environment with this feature. Some of the possible issues to be addressed can be the following:
1. what is an intuitive and efficient representation for a continuous time
system in the context of the Metropolis meta-model? Are the metropolis black
box structures adequate?
2. What should an interface between a continuous time block and the rest of
the simulator be structured?
3. Can sensors and actuators be seen as refinements of a communication medium?
4. How is it possible in a simulation environment to deal with events
generated from a continuous time system?
These issues should be investigated thoroughly and the effectiveness of the solution shown on a simple example. An ambitious goal could be to translate the design of this simple case study into the Ptolemy II XML format and validate the result using the simulation environment embedded in this package.
Mentors: Yosinori
Watanabe (watanabe@cadence.com)
Luigi Palopoli (luigip@eecs.berkeley.edu)
Claudio Pinello (pinello@eecs.berkeley.edu)
Assigned to:
http://www.cs.berkeley.edu/~yatish/ee249/index.html
In the software-based design methodologies for embedded systems, systems
are designed and programmed in a functional computation model. This can be
finite state machines, data flow networks, Petri nets, Descrte events, etc.,
depending on the target application. Software synthesis techniques are used to
derive implementation code, like C, from these models.
We are interested in the finites state machine model, derived from high-level
language Esterel. Currently, the automatically generated code is not
competitive in terms of execution speed, because the control portion (up to
90%) runs slow on normal ALU-based architectures.
This project studies an architecture platform (possibly reconfigurable), where a coprocessor is dedicated for executing the control portion of the code. One idea is to use FPGA to configure and execute the control code. Another idea is to use memory to load blocks of control functions and evaluate the output (ref[1]). The key, in general, is the interface between the ALU and the coprocessor.
We would use MVSIS (ref[2]) to generate C code from Esterel, and use a specialized version of compiler/profiler gcc to simulate/profile the performance of the proposed architecture.
References: [1] Tsutomu SASAO, Munehiro MATSUURA, and Yukihiro IGUCHI,
"A Cascade Realization of Multiple-Output Function for Reconfigurable
Hardware", IWLS 2001.
[2] M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, S. Sinha, And R.K. Brayton, "MVSIS",
IWLS 2001. [3] "A Software Development Tool Chain for a Reconfigurable
Processor", Alberto La Rosa, Luciano Lavagno and Claudio Passerone, CASES
2001.
Mentors: William Y. Jiang (wjiang@EECS.Berkeley.EDU)
Luciano Lavagno (luciano@ic.eecs.berkeley.edu)
Assigned to: Yatish Patel and Frank Gennari
ECL is a language for control-dominated system-level design that builds upon the Esterel semantics foundation, and adds C-style syntax, data types and control structures. The existing compiler takes in ECL code and produces Esterel code and C functions to be called by it.
This project is aimed at using a portable debugger interface (e.g. deet, ddd or others) in connection with the software code generated by the ECL compiler. This is C code that currently has debugging hooks that stop the execution every time a source statement is hit, and can access memory to display the value of variables.
The task is to develop an interface between that mechanism and one of these standard debuggers, to allow source-level debugging (breakpoints, watchpoints, variable display) for ECL.
Skills: java (and possibly a bit of C) programming.
Mentors: Ellen Sentovich (ellens@cadence.com
)
Luciano Lavagno (luciano@ic.eecs.berkeley.edu)
Roberto Passerone (roby@eecs.berkeley.edu
)
Assigned to:
ECL is a language for control-dominated system-level design that builds upon the Esterel semantics foundation, and adds C-style syntax, data types and control structures. The existing compiler takes in ECL code and produces Esterel code and C functions to be called by it.
This project is aimed at interfacing the existing ECL compiler (written in Java) with a compilation infrastructure from Esterel to C, written on top of the SUIF-2 compiler creation framework by Steve Edwards (formerly Synopsys, now Columbia University).
The task is to modify the existing compiler so that, instead of writing out Esterel and C as separate pieces of code, it writes the SUIF internal database for both kinds of constructs, so that Edward's compielr can then generate scheduled C for the full ECL program.
Skills: java (and a bit of C++) programming.
Mentors: Ellen Sentovich (ellens@cadence.com
)
Luciano Lavagno (luciano@ic.eecs.berkeley.edu)
Roberto Passerone (roby@eecs.berkeley.edu )
Assigned to:
http://embedded.eecs.berkeley.edu/~yinghua/ee249/project.html
ECL is a language for control-dominated system-level design that builds upon the Esterel semantics foundation, and adds C-style syntax, data types and control structures. The existing compiler takes in ECL code and produces Esterel code and C functions to be called by it.
The aim of this project is to add capabilities for RTL hardware modeling to ECL, following guidelines for Esterel extensions developed by Berry and others. These extensions include bit vectors and matrices, equational notation and so on.
The task is to extend the ECL parser with 5-10 constructs to handle these extensions, and generate the appropriate Esterel and C code when these are used.
Skills: java programming.
Mentors: Ellen Sentovich (ellens@cadence.com
)
Luciano Lavagno (luciano@ic.eecs.berkeley.edu)
Roberto Passerone (roby@eecs.berkeley.edu )
Assigned to: Huifang Qui and Yinghua Li
Formal semantics of metropolis meta-model is being developed. The semantics is automata based, i.e. for each syntactic construct in the meta-model, we define an automaton specifying its semantics. The goal of this project is be able to automatically generate these automata for a meta-model netlist. Ideally, automata would be specified in an analyzable format, e.g. SMV. Then they could be used as an abstraction for formal verification.
Mentors: Felice Ballarin (felice@cadence.com )
Assigned to:
Part of Metropolis meta-model is a set of constraints that could be specified in a logic called LOC (Logic Of Constraints). It has been suggested that it is possible to generate a simulation monitor that checks whether an LOC formula is violated. However, the existing suggestion is sketchy and many details and efficiency considerations are not clear yet. Your goal is to find a way to efficiently implement such a monitor. Could be a joint project with 12).
Mentors: Felice Ballarin (felice@cadence.com )
Assigned to:
Part of Metropolis meta-model is a set of constraints that could be specified in a logic called LOC (Logic Of Constraints). Not all LOC formulas can be represented by FSMs, but some of theme can. Your goal is to define a subset which may be converted to FSMs and to develop the conversion procedure. Alternatively, you may try to find a conversion procedure from an LOC subset to a decidable temporal logic like LTL. Could be combined with 11).
Mentors: Felice Ballarin (felice@cadence.com
)
Assigned to:
http://www.stud.ntnu.no/~tronarne/EE249/proj.html
The TSM is a denotational framework for comparing models of computation. In a typical control system sensors and actuators transform signals from one MOC to signals into another MOC, e.g. continuous values of a temperature are sampled and quantized into a sequence of integers.
The students will use the TSM to model a specific sensor+filter ensemble typically used in automotive engine control: the flywheel position encoder. On the flywheel peripheral there is a series of teeth coupled with a magnetic sensor, they serve as a position encoder. A tooth is missing so that a ZERO position can be recognized. Processing the output waveform, the filter can reconstruct the crankshaft position, a critical state variable used for most engine control tasks e.g. fuel injection and spark ignition.
The students should first model the sensor, then they should use FSMs and DataFlow to design and model a valid filter. Finally the interactions among the flywheel, FSMs and DataFlow should be modeled and analyzed using the TSM. Particularly valuable would be an analysis of robustness with respect to noise.
Number of people: 1-2 students
Mentors: Andrea Balluchi (balluchi@parades.rm.cnr.it)
Claudio Pinello (pinello@eecs.berkeley.edu)
Massimo Baleani (mbaleani@eecs.berkeley.edu)
Assigned to: Tron Nilsen
http://www-inst.EECS.Berkeley.EDU/~xuanming/ee249/ee249.html
A Petri-Net based method for synthesizing code for the software component of a system is proposed in [1]. The specification is given as a set of concurrent processes that communicate through channels. Each process is a sequential program that may contain data-dependent control statements.
The synthesized software consists of a set of tasks. A task is generated by analyzing the computation associated to the occurrence of an event at each input port connected to the environment. The task generation and scheduling algorithm guarantees that task execution can be performed with a finite amount of inter-task buffer memory under arbitrary input streams.
Paper [1] uses transition-invariants in finding sequences of transisitons that can be fired from a given node (marking) of the reachability tree. In general, there are many firable sequences for a given marking, and we currently choose one using some heuristic. In order to reduce the schedule size, it is better to choose one that has been already used. For example, if a sequence s1 has been used from a node n1, and if s1 is included in the set of firable sequences from another node n2, then it is better to choose s1 at n2. This is not currently accounted for in the heuristic of [1]. The general question is what would be the set of sequences of transitions that should be used in composing a schedule so that the size of the composing a schedule so that the size of the schedule is minimum. This project aims to generate a better quasi static schedule from concurrent processes by new method.
[1] J. Cortadella, A. Kondratyev, L. Lavagno, M. Massot, S. Moral, C. Passerone, Y. Watanabe and A. Sangiovanni-Vincentelli, Task Generation and Compile-Time Scheduling for Mixed Data-Control Embedded Software, Proc. 37th Design Automation Conference, Los Angeles (USA), June 2000, pp. 489-494.
Mentors: Yosinori Watanabe
Assigned to: Cong Liu and Xuanming Dong
http://robotics.eecs.berkeley.edu/~cedricma/ee249/project.html
The main objective of our project is to utilize the Platform-Based Design paradigm to establish a design methodology for UAV systems controlled by synchronous embedded programs.
Currently, many synchronous embedded control programs are written specifically for a particular set of sensors and actuators belonging to the system-under-test. Since these sensors and actuators can vary greatly in the type of interfaces they provide, and that the data types may be extremely complicated, the control program will have to be extensively modified every time a new suite of sensors or actuators are used.
Our goal is to define a "virtual avionics platform" which will bridge the gap between (1) the UAV sensor/actuator, computing, and communication devices, and (2) the embedded control program. This "virtual avionics platfrom" will present an API to the control programmer that will allow the control program to be written independent of the particular physical sensors, actuators, and computing platform chosen.
We demonstrate the application of this design methodology for UAVs by implementing (1) a synchrnous embedded controller, (2) the virtual avionics platform, and (3) simulated dynamics of a UAV with an appropriately modeled sensor/actuator suite. The embedded controller and the virtual avionics platform will run on a separate computer (the "Controller") from the one that simulates the UAV dynamics (the "Simulator"), so that (in future research) the "Controller" can be used readily to fly the physical UAV itself instead of a simulated version of it. The synchronous embedded language we will use is Giotto, and easily lends itself to the control objecive. Finally, way-point navigation of the UAV will be demonstrated using a 3-D visualization tool.
Mentors: Cedric Ma and Judy Liebman
http://www.cs.berkeley.edu/~densmore/CFTRS.htm
The purpose of this project would be to explore the design issues when constructing a subclass of embedded systems we have defined as External Input Fault Tolerant Reactive Control Systems (EIFTRCS). A loose definition of a EIFTRCS would be a reactive control system that provides external input fault tolerance for another system. For example, let system A serve as a EIFTRCS for system B. A inputs include B inputs plus environmental sensor inputs. If B inputs are found to be faulty when compaired with environmental sensor inputs, A outputs supply alternate non faulty inputs for system B.
This project would involve creating a formal set of requirements and constraints to consider when designing a EIFTRCS. This would result in a formal EIFTRCS model and method of expression.
This model could then be used to implement a simple case "real world" system like crash avoidance in a radio-controlled car.
Mentors: Doug Densmore and Shannon Zelinski
Giotto is an abstract programmer's model for the implementation of embedded control systems with hard real-time constraints. Giotto supports the automation of the control system design process by separating platform-independent functionality and timing concerns from platform-dependent scheduling and communication issues. Giotto consists of a time-triggered programming language, a compiler, and a virtual real-time scheduling machine called the embedded machine. The basic functional unit in Giotto is a periodic software task. A Giotto mode is a set of tasks and mode switches. A Giotto program is a set of Giotto modes with one mode being the start mode. A Giotto system can only be in a single mode at the same time. Given a Giotto program, the Giotto compiler produces embedded machine code that supervises the real-time execution of the tasks in each mode. The existing Giotto compiler generates an executable that has to be linked against the embedded machine implementation. This means that currently a Giotto program specifies the system behavior in a static manner, that is, it can only exhibit behavior that has been anticipated at design time. However, changing system behavior at run time is a highly desirable feature for many applications. The goal of the project is to study the potential of the embedded machine concept for changing system behavior at run time. For instance, new Giotto modes may be uploaded to the embedded machine similar to dynamic class loading in Java. The first step of the project is to decide on the binary format for embedded machine code and to change the back-end of the existing Giotto compiler accordingly. The next step would be to implement the embedded machine code uploading mechanism. The difficult part is to link dynamically new code segments to existing code.
Mentors: Prof. Henzinger
Assigned to: Arkadeb Ghosal and Slobodan Matic
http://embedded.eecs.berkeley.edu/~arindam/interface.html
I am currently working in the field of software verification under the guidance of Prof Henzinger. I am interested in interface automata, a formalism for expressing temporal constraints defining software component interfaces. We believe that this formalism can be profitably applied to automatic compatibility checking of a large class of software systems, and to embedded software in particular. This is thus a promising aspect to study from the point of view of embedded system design. We propose to study the issue of design by contract and evaluate solutions proposed by several groups engaged in studying this problem. We plan to develop a language that will allow programmers to naturally express interface constraints of their modules under development and to incorporate interface checking as a part of a popular Java IDE, JBuilder.
We believe that the interface formalism will be suitable for describing a large variety of software systems like embedded software modules, web servers, device drivers etc. We have studied the TinyOS system (operating system for SmartDust) and found a good interface automata model for it.
We plan to incorporate interface checking into a popular Java IDE like JBuilder which can be used to provide the benefits of this verification approach to programmers in a transparent manner. For this we need to design a language in which programmers might be able to naturally express the interface that they expect their module-under-development to respect.
A more ambitious aim is to design and implement a low cost strategy to automatically check that the component respects the interface that the software developer writes for it.
References
[1] Interface Automata, by Luca de Alfaro and Thomas A Henzinger,
to appear in the Proceedings of the 9th Annual ACM Symposium on Foundations of
Software Engineering (FSE), 2001. [2] Interface Theories for Component-based
Design, by Luca de Alfaro and Thomas A Henzinger, Proceedings of the First
International Workshop on Embedded Software (EMSOFT), 2001 [3] Jass - Java
with Assertions, by D Bartetzko, C Fischer, M Moller, and Heike Wehrheim,
Electronic Notes in Theoretical Computer Science http://www.elsevier.nl/locate/entcs
[4] Behavioral Contracts and Behavioral Subtyping by R B Findler, Mario
Latendresse, Matthias Felleisen, FSE 2001 [5] jContractor: A Reflective Java
Library to Support Design by Contract by M Karaorman, U Holzle, J Bruno http://www.cs.ucsb.edu/~murat/jContractor.PDF
[6] iContract - The Java Design
by Contract Tool by Reto Kramer Technology of Object Oriented Languages and
Systems, 1998 [7] Adding Contracts to Java with Handshake by A Duncan, u
Holzle Technical Report TRCS98-32, UC Santa Barbara, 1998 [8] The Contracts
Reading List http://www.cs.rice.edu/~robby/contract-reading-list/
[9] Eiffel:
The Language by B Meyer, Prentice Hall, 1992 [10] Design by Contract Using
JMSAssert http://www.mmsindia.com/DBCForJava.html
Mentors: Marcin Jurdzinski, Freddy Mang, Tom Henzinger, Luca de Alfaro
Assigned to: Arindam Chakrabarti
http://www.eecs.berkeley.edu/~rcshah/ee249.htm
PicoRadio is an ongoing project at the Berkeley Wireless Research Center that is trying to develop tiny meso-scale nodes capable of forming ad-hoc networks. The key challenges in the project are the small form factor and energy constraints at every node. For this, we need smart protocols that are energy efficient while meeting all requirements of the application. To test the behavior of the protocols that are developed, we are currently defining the protocol stack in VCC. This enables us to simulate the functional behavior of the routing, medium access and data link protocols. However, the complexity of the data link layer precludes us from simulating a large network of such nodes and checking the performance of the protocols in terms of their energy consumption and timing characteristics.
For this project, we plan to fully define the data link and MAC layer of the PicoNodes and create a small network of 5-6 nodes. We then want to use VCC Architectural Services to provide a performance characterization of the data link protocol layer. Since the data link layer does not need an entire network to test, a few nodes should provide a fairly accurate characterization. Also, this is the most complex part of the protocol stack, thus we clearly need to understand whether the sub-blocks can meet the required constraints. Using this characterization, we can explore different target architectures and try to obtain an architecture that is efficient as well as meets all the constraints of the protocol operation. This is crucial for the design of the next generation PicoNode. At the same time, this will help in defining new services VCC needs to support for simulating such large-scale embedded systems.
Mentors: Mei Xu and Rahul Shah
http://ptolemy.eecs.berkeley.edu/~celaine/ee249/
TinyOS [1] is an event based operating environment designed for use with embedded networked sensors. It is designed to support the concurrency intensive operations required by networked sensors with minimal hardware requirements. TinyOS currently runs on the Smart Dust "macro motes" [2] [3]. "Macro motes" are large scale models for Smart Dust that incorporate communications, processing, sensors, and batteries into a package about a cubic inch in size using commercial-off-the-shelf components.
We plan to study the TinyOS architecture and formalize its programming model in a Ptolemy domain. We also plan to compare TinyOS to models of computation such as Giotto [4] and other patterns for distributed systems [5], such as the Reactor pattern. We will investigate building hierarchical models on top of our new domain. We will also explore potential applications for this new domain and the possibility of mapping the models to TinyOS via code generation in Ptolemy.
[1] http://tinyos.millennium.berkeley.edu/
[2] http://robotics.eecs.berkeley.edu/~pister/SmartDust/
[3] http://www-bsac.EECS.Berkeley.EDU/~shollar/macro_motes/macromotes.html
[4] http://embedded.eecs.berkeley.edu/~fresco/giotto/
[5] http://www.cs.wustl.edu/~schmidt/POSA/
Mentors: Elaine Cheong, Yang Zhao
www.cs.ucla.edu/~farinaz/249project.htm
The overall goal of this project is to create an approach for developing effective and efficient distributed applications, and more specifically distributed practical algorithms for wireless (ad-hoc) sensor networks. I can briefly outline the global picture of the approach in the following way: The first step is to partition the network on which the problems will be solved in number of regions efficiently. Each region will solve its part of the overall problem independently. The key point is that each individual solution should be flexible, in a sense that it should easily accommodate to consequent needs for change through local action. In particular, nodes that are on boundary of regions are one for which we will provide high level of flexibility. The overall goal is not to find the best optimal solution, but to find specific distributed maximally constraint minimally constraining distributed procedure. One of the major trade-offs to study would be communication/ computation trade-offs between fully distributed and clustered or possibility of having larger clusters.
Mentors: Farinaz Koushanfar
http://www.cs.berkeley.edu/~kaushikr
MoML is an architectural, structural description language produced by Ptolemy, which is being leveraged by the Mescal research group. MAD (Mescal Architectural Description) is a language used specifically to describe architectures such that they may be mapped to a compiler and a simulator. Currently, Liberty, developed at Princeton, is used as this compiler and simulator. But there is a missing link between MAD and MoML to allow architecture described in MoML to be expressed in MAD. The goal of this project is to extend MoML to contain the missing information needed by MAD (e.g. pipelining, semantics, behavioral, etc.). This will involve defining new structures for MoML, a GUI interface in the MoML entry application, and a translator from MoML to MAD.
Mentors: Kaushik Ravindran Will Plishker
Communication among components of a design has become a first class citizen since it impacts the correctness of the design and its cost in a substantial way. SOC designers are often too focused on the physical aspect of the communication problem neglecting the high-level view that could in fact offer a much better final implementation with cleaner interfaces and better performance. The project goal is to analyze the communication problem from the behavioral point of view marching towards the implementation using successive refinement and identify all intermediate layers that could facilitate the design process. As a result of the study, a communication architecture design platform will be identified. The analysis process that we are going to follow is strictly related to the Metropolis framework and to the principles of communication-based design.
Mentors: Alessandro Pinto, Gerald Wang
http://inst.eecs.berkeley.edu/~perlegos/ee249/ee249.htm
The basic goal of this project is to implement the PicoRadio protocol using
the Metropolis meta-model. I will use the application that consists of a set
of sensors (S), controllers (C), and actuators (A). The interaction between S
and C has two scenarios. The first is the Pull scenario in which controllers
request data to a set of sensors upon requests from an external user. The
second is Push in which sensors send data to controllers periodically. The
interaction between C and A has only one scenario in which the controllers
issue commands to actuators. At the application layer level, each pair of
interacting S, C, and A are connected by a reliable medium of one-hop links.
This link is refined at the network layer into a multi-hop connection, where
any node can be used as an intermediate hop in a path from source to
destination. This multi-hop connection is essential to maximize reuse of
resources and reduce power consumption. I will implement this protocol using
Metropolis to specify both the behavior and structure. This includes
specifying the behavior of each block and the connections between them at each
successive layer. For project updates or for more information about my
project, please see my project webpage:
http://inst.eecs.berkeley.edu/~perlegos/ee249/ee249.htm
Mentors: Marco Sgroi
Assigned to: Pete Perlegos