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![](satnam_files/satnam.singh.jpg)
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Co-Design and
Co-Verification using
a Synchronous Language
Monday, Oct.
13th,
2003, 4pm - 5pm
540A/B Cory Hall (D.O.P. Center Classroom)
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Abstract
Is it possible to
implement control-based algorithms in hardware for fast execution using a design
method that has the flexibility and rapid development properties of software? At
Xilinx Research Labs we are trying investigating the synchronous reactive
programming language Esterel and its suitability as a hardware description
language. We will present initial results showing how certain types of
control-based computations can be implemented efficiently either in hardware (using
FPGA fabric) or software (using embedded PowerPC405 processors or soft
processors) from the same specification cast in Esterel. The examples we looked at include
standard serial peripherals, simple video games, hardware based mutual
exclusion, link-layer protocols and components of ten gigabit ethernet MACs. The
presentation will focus on the results of using this approach for co-design and
will also present some advantages of this approach which permit formal analyses
for performing safety property checks on protocols using model checking.
Speaker
Satnam Singh
obtained his PhD in 1991 at the University of Glasgow in formal techniques for analyzing
hardware description languages. After serving as a faculty member in the EE and
CS departments at the same university he joined Xilinx's research
laboratories in 1998. He has worked on the Lava hardware description language http://www.xilinx.com/labs/lava;
high level support for dynamic
reconfiguration; advanced techniques for hardware verification; and novel techniques system level
design and modeling.
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