Analytical Approach To Interconnect Optimization

Abstract

Buffer insertion, buffer sizing, and wire sizing are useful techniques for improving circuit performance. For high performance designs, existing algorithms need to chop a long wire into many small segments in order to obtain a large set of possible buffer locations and to achieve non-uniform wire width along the wire. Consequently, the number of variables in the optimization problem is increased substantially and thus results in long runtime and large storage. In this talk, we present an entirely different approach to the problem. Instead of chopping a wire into many small segments, we analytically determine buffer locations, buffer sizes, and wire widths. Our algorithms are fast enough that they can be used during the early chip planning stage.