Coverage Directed Validation of Hardware Models


Currently validation of the initial HDL description and verifying the design in different levels of abstraction against each other is a major bottleneck in the design process. Because the HDL description is usually the first description of the design, simulation is the primary methodology for validating it. Simulation-based verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. This talk provides the details of an efficient method to compute an Observability-based Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs. It also introduces a new method for generating test vectors under any coverage metric.

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