Layout-Driven Logic Optimization
In this talk, I will present a new paradigm for solving the timing convergence problem for designs in the deep sub-micron technologies. The paradigm includes a modified design flow in which logic optimization is interleaved with placement/partitioning refinement and hierarchical global routing. The optimization incorporates a comprehensive set of layout-friendly, logic-level transforms for improving the delay and area of a mapped, block-placed, and globally routed circuit under design and technology constraints. We have implemented this paradigm at Fujitsu Labs in an industrial-strength design tool, which has been applied successfully on several industrial designs. Along with the practical aspects, I will also present a couple of theoretically interesting sub-problems in net buffering and gate resizing.
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