Electronic Systems Design Seminar


Global Signaling Strategies for Nanometer CMOS

Prof. Dennis Sylvester
EECS, University of Michigan

Friday, April 12, 2002, 11:00am-12:00pm
540AB Cory Hall (DOP Center Classroom)



The current global signaling paradigm in high performance digital IC's consists of static CMOS buffers/repeaters inserted uniformly along long global routes to reduce wire RC delay. This approach does not scale well - more global routes combined with more resistive interconnections yield a roughly cubic increase in the number of repeaters needed in each technology generation. The power consumption of these buffers is appreciable and causes power distribution and via proliferation problems as well.

To address this, we have developed two new signaling approaches that are complementary to the existing CMOS repeater paradigm. First, transition-aware global signaling (TAGS) is aimed at reducing the number of repeaters on global lines. Preliminary results focused on noise immunity properties while confirming superior power/area properties at a fixed delay. Despite the fact that this techniques senses transitions early and enforces them, the noise rejection properties of the TAGS receiver are excellent, resulting in better overall noise characteristics than repeaters. The second approach is aimed at using the large coupling capacitances present in today's processes to speed up switching of long interconnects. Rather than having these capacitances potentially slow down a critical signal, we propose the use of active shields. As opposed to conventional (passive) shielding, the active shielding approach helps to speed up signal propagation on a wire by ensuring in-phase switching of adjacent nets.


Dennis Sylvester received his Ph.D. in electrical engineering from the University of California, Berkeley, in 1999. After working as a Senior R&D Engineer in the Advanced Technology Group of Synopsys, he is now an Assistant Professor of Electrical Engineering and Computer Science at the University of Michigan. His research interests include interconnect characterization and modeling, low-power circuit design techniques, and variability-aware circuit design and analysis.

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