Electronic Systems Design Seminar
http://www-cad.eecs.berkeley.edu/esd-seminar

Abstract

The SCALE project is developing a new "all-purpose" VLSI architecture for future embedded and general-purpose systems. Despite the ample parallelism present in many applications, existing processors are hampered by serial instruction sets and can only execute a handful of instructions per cycle. SCALE introduces a new parallel instruction set paradigm, vector threading, which supports many forms of fine-grain parallelism from pure SIMD data parallelism to pure MIMD thread parallelism, at low cost and with low power dissipation. For many applications, power consumption will be the primary constraint on system performance, cost, and size. A major emphasis in the SCALE project is the development of new techniques that give software fine-grain control over processor energy usage. By exposing hardware energy consumption to software, we can exploit compile-time knowledge to reduce run-time energy dissipation. This talk will present an overview of the SCALE project and the design of the SCALE-0 microprocessor prototype under development at MIT.

Speaker

Krste Asanovic is an Associate Professor in the EECS Department at MIT and a member of the MIT Laboratory for Computer Science. Prof. Asanovic received a bachelor's degree in Electrical and Information Sciences from Cambridge University in 1987 and a doctorate in Computer Science from the University of California, Berkeley, in 1998. At MIT, he leads the SCALE project. From 1987-89 he was at the GEC Hirst Research Center in London where he co-architected the SPACE associative processor containing over 170,000 SIMD processors. At Berkeley, he led the development of the TO vector microprocessor and was an early contributor to the Berkeley IRAM project. He is currently serving as a member of the technical program committees for the International Solid-State Circuits Conference and the International Symposium on Computer Architecture. He is also serving as a DARPA ISAT member.