Electronic Systems Design Seminar

Bart Kienhuis

System design using Kahn Process Networks -
The Compaan/Laura Approach

Bart Kienhuis, Assistant Professor
Leiden Embedded Research Center
Leiden University, the Netherlands

Tuesday, May 13th, 2003, 4:00pm - 5:00pm
540AB Cory Hall (DOP Center Classroom)

This is a joint seminar with Chess.


High-performance and domain specific embedded architectures, composed of microprocessors, memories, and a number of dedicated coprocessors are very hard to program. On these architectures, applications will be executed that belong to the domains of (real-time) multi-media processing, mobile communication, encryption, or adaptive array processing. These applications are often written in a particular way in C or more and more the Matlab language. The computational model of C, however, does not fit the described architectures making the programming of these architectures a tedious task. On the architectures, instruction level parallelism can be used effectively but not task-level parallelism. To exploit task-level parallelism, a better specification format would be to use an inherently parallel model of computation like Kahn process networks.

In the presentation, we will explain the Kahn process network model of computation in more detail and indicate why this model is interesting for System design of stream-oriented applications. Next, we present our design methodology by presenting the Compaan/Laura compilers. The Compaan compiler derives from a subset of Matlab - so called nested loop programs - automatically process network descriptions. The obtained network models are formatted in the Ptolemy II actor model or in C++ using the YAPI model for functional simulations. After this, the Laura compiler converts the network descriptions to VHDL, such that the networks can be mapped directly onto FPGAs. We conclude the presentation by showing a case in which we converted the MJPEG application into a process network description and map some of the processes on a CPU and other processes on the FPGA.


Bart (A.C.J.) Kienhuis received his MSEE from Delft University of Technology in 1994 and he received his Ph.D. from Delft University of Technology in 1999. During his Ph.D., he has worked at Philips Research Laboratories in Eindhoven on a design methodology (the Y-chart approach) for high performance video architectures for consumer products. From 1999 until 2000, he was a Post Doctoral researcher in the group of Prof. Edward A. Lee at the University of California at Berkeley. He is currently an assistant professor in the Leiden Embedded Research Center, at LIACS, Leiden University, where he runs the Compaan Project. His primary interest is in the area of Embedded System design with an emphasis on design space exploration and platform based design.

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