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Electronic
Systems Design Seminar
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Architecture-Level Synthesis for Automatic Interconnect Pipelining
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For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined global interconnects. In this paper we present an architecture-level synthesis solution to support automatic pipelining of on-chip interconnects. Specifically, we extend the recently proposed Regular Distributed Register (RDR) micro-architecture to support interconnect pipelining. We formulate a novel global interconnect sharing problem for global wiring minimization and show that it is polynomial time solvable by transformation to a special case of the real-time scheduling problem. Experimental results show that our approach improves the conventional approach by 38% on average in terms of the clock period and 31% improvement on average in terms of the final latency, which matches or exceeds the RDR-based approach in performance, but with a significant wiring reduction of 15% to 21%.
Jason
Cong received the M.S. and Ph.D. degrees from the University of
Illinois, Urbana-Champaign, in 1987 and 1990, respectively, all in
computer science. Currently, he is a Professor and Co-Director of the
VLSI CAD Laboratory in the Computer Science Department, University of
California, Los Angeles. He has been appointed as a Guest Professor at
Peking University since 2000. His research interests include
layout synthesis and logic synthesis for high-performance low-power
VLSI circuits, design and optimization of high-speed VLSI
interconnects, field-programmable gate array (FPGA) synthesis, and
reconfigurable computing.