EECS 298-11: CAD Seminar
Wednesday, May 3, 5pm
531 Cory Hall, Hogan Room

                  Some problems in submicron technology
             and their effect on design methods and CAD tools

                            Antun Domic
                       Cadence Design Systems

The reduction in feature sizes for semiconductor technologies continues to
advance: CMOS transistor channel lengths are now below 0.5 microns.  We have
available new possibilities in terms of the complexity and speed of designs
that can be put into one chip. But we are facing new problems: productivity
needs to advance significantly if reasonable sized teams can take advantage of
these capabilities, and the new technologies introduce different problems that
will bring important changes in the way we design.

Two problems will be discussed from an industry perspective. The first is
productivity in HDL based design and possible approaches to improve it. The
second is the increased relevance of physical effects and the ways these may
change how CAD tools, particularly synthesis tools, are used.


Future Seminars:

May 5    - Georges Gielen, KU-Leuven (Special seminar, Friday, 2PM)
           "Research Developments in Analog CAD at KU-Leuven"

May 10   - Stan Liao, MIT
           "Code Generation and Optimization for Embedded DSP Processors"

End of semester