EECS 298-11: CAD Seminar Wednesday, May 17, 5pm 531 Cory Hall, Hogan Room Symbolic Analysis for Large Analog ICs Carl Sechen Universty of Washington If you have ever designed a new analog circuit topology or even analyzed an analog circuit in an undergraduate course, you probably know what a chore it is to have to manually grind out a symbolic expression for a transfer function or an impedance of a linearized (about a bias point) model of the circuit, even for very small circuits. However, due to some recent research results, an efficient computer program is now available which can handle quite large circuits. In fact, we apparently have the ability to generate symplified yet accurate symbolic expressions for any size circuit for which we can still interpret (make sense of) the resulting expressions. Our approach is based on the classical two-graph tree enumeration method and is outlined below: First, a two-graph consisting of a voltage graph and a current graph is constructed for both the numerator and the denominator of the network function such that each product term in the cancellation-free symbolic expression corresponds to a common spanning tree of the two-graph and is called a tree admittance product. Second, a sensitivity-based simplification is carried out in which the two-graphs are simplified by edge contraction and deletion based on the numerical contribution of circuit elements for these edges to the network function. Finally, only the product terms with the largest magnitude in the expression, called significant product terms, are computed by generating the common spanning trees of the simplified two-graphs in decreasing order of their tree admittance product until certain error control criteria are satisfied. We directly generate common spanning trees of the two-graph in decreasing order of tree admittance product using matroid intersection algorithms. Theoretically, our strategy reduces the total computation time for generating an approximate symbolic expression in expanded non-hierarchical format to polynomial with respect to the size of the circuit and the number of sample frequencies in the range of interest, assuming the number of product terms retained in the final expression is polynomial with respect to the same variables. This has not been achieved by any previously reported approximation strategies. Future Seminars: June 2: Ed Clarke, CMU End of semester