EECS 298-11: CAD Seminar
Wednesday, January 31, 1996, 5pm
531 Cory Hall, Hogan Room



Design Replacements for Sequential Circuits
(Ph.D. Dissertation Talk)
 
Vigyan Singhal
Cadence Berkeley Labs
 
 
A notion of design equivalence or design replacement is crucial for
problems of logic synthesis and verification.  For sequential
gate-level or state-graph-level circuits, the "right" notion
of design replacement is not obvious, especially for arbitrary pieces
of logic which may not have a well-defined initial state.
We will illustrate how many existing notions of replacement
implictly make assumptions about the environment.  We will illustrate
safe replaceability, which is one notion of design replacement which
does not make these assumptions and is intended to work for any piece
of sequential logic embedded in an arbitrary larger design.  To explore
the flexibility in behavior for the initial few clock cycles after
power-up, safe replaceability could be substituted by delay
replaceability.  We will also show how the semantics of a simulator
are closely tied to the "right" notion of design replacement. The
semantics of the simulator may allow a designer to make replacements
which are more aggressive than replacements based just on the behavior
of the design;  alternately, it may require a more conservative replacement.
 
In addition, some of the following will be addressed:
 
- complexity of the verification problem for safe (delay) replaceability
- algorithms for synthesis using safe and delay replacements
- obtaining the initial states of retimed flip-flops



Upcoming Seminars:

   Feb 7: Robert P. Kurshan, AT&T Bell Labs
	  "Hardware Verification at AT&T"

   Feb 12(5pm): Francesco Piazza, Swiss Federal Institute of Technology

   Feb 14(3pm): Miron Abramovici, AT&T Bell Labs
	  "Identifying Sequential Redundancies Without Search"

   Feb 14: Scott Hauck, Northwestern University
	  "Multi-FPGA Systems"

   Feb 21: Alex Saldanha, Cadence Berkeley Labs