EECS 298-11: CAD Seminar Wednesday, May 7, 1997, 5pm Cory Hall--Hogan Room High Level Power Optimization and Analysis Techniques Sujit Dey C&C Research Laboratories NEC USA Low power designs are becoming increasingly critical, driven by a variety of requirements such as prolonging battery life in portable devices, and reducing chip packaging costs. Addressing power consumption starting at the higher levels results in large power savings, and fewer and faster design iterations. In this talk, I will present some RT-level power optimization and analysis techniques that we have developed for control-flow intensive designs like networking and controller applications. I will first discuss the characteristics of control-flow intensive applications, and the requirements for low-power design and analysis of such applications. Next, I will present RTL power optimization techniques that minimize glitching power and apply power management, and an RTL switching activity and power estimation technique. Recognizing the fact that glitching can account for a large portion of the total power, we have developed techniques to transform a given RTL circuit to minimize the generation and propagation of glitches through the circuit. We have also developed low-overhead power management techniques, which exploit idle conditions for various circuit blocks to eliminate unnecessary power dissipation. Our power estimation technique utilizes a combination of bit-level and word-level macro-modeling for the data path logic, and analysis techniques that use functional and partial delay information for the control logic. Application of the power optimization and analysis techniques to several RTL circuits demonstrates their effectiveness to significantly reduce power consumption and obtain accurate power estimates.